Job Title: Business Development Manager – Imaging Partner

The business development team is responsible to identify and develop strategic partners for existing and new businesses. The ideal candidate for this position should have 3+ years of marketing experience in mobile imaging market, and ideally be familiar with mobile camera ecosystem and imaging technologies.

ESSENTIAL DUTIES AND RESPONSIBILITIES include the following. Other duties may be assigned.

• Manage and grow the relationship with existing partners
• Develop new partners
• Develop and implement marketing plans and events with partners
• Work closely with R&D team to build marketing packages for imaging products
• Manage all imaging deliveries including the processing of deliveries and the management of the delivery build
• Gather requirements and feedback from partners to R&D team to improve the product

QUALIFICATIONS

Bachelor's degree in computer science or electrical engineering and 5+ years of relevant work experience. Master’s degree is a plus. Excellent communication and presentation skills in English are a must. Ability to read, write, analyze, and interpret the English language is essential; the ability to speak Mandarin is a big plus.

Additional Required Skills

• Familiar with mobile camera ecosystem, ISP, and imaging processing technologies
• The ability to craft a story and articulate it to executive audiences, both internal and external.
• The ability to impact and influence and drive results through others.
• Cross-boundary collaboration with strong interpersonal skills and adeptness in working across functional areas.

urgent position to be fulfilled is a ASIC design verification engineer. It needs experiences in CPU design. The JD is as below.

(Sr.) ASIC Design Verification Engineer

Position Description:
As part of the IP design team, the candidate will be responsible for the pre-silicon verification of in-house designed micro-processor which is a built-in component for next generation video codec IP, including:
· Build up and maintain verification environment, including development of testbench and test generators for block-level and full-chip level simulation;
· Develop and execute functional verification test plans, include writing tests, developing behavioral checkers and coverage/code monitors; Analyze coverage gaps and devise strategies to fill coverage holes;
· Work with designers to debug failing tests and resolve bugs;
· Help develop and maintain flows/scripts/tools for front-end design/verification;

Qualification:
· BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;
· Self-motivated team player, with strong problem resolving skills;
· Proficient and experienced in high-level verification methodology (VMM/UVM/OVM), Verilog-HDL, and hardware verification language (SystemC/SystemVerilog);
· Familiar with video coding standard, and/or computer architecture/micro-architecture;
· Hands-on experienced in CPU verification, including test plan and test bench development, test case development and test coverage assessment would be a great plus;
· Experiences in assembly programming, and using scripting languages (Perl/Tcl/Bash/Csh) for flow automation;
· Familiar with front-end ASIC design flow;

Position: (Sr.) ASIC Engineer of SOC and Video system

Responsibilities:

- SOC

n Chip architecture define and coordinate including clock/reset structure definition, low power partition definition, etc

n STA (define SDC and sign off timing)

n Low power (define UPF/CPF, verify low power structure from RTL to netlist)

n Understand DFT/synthesis flow, provide necessary support

- Design

n IP level micro-architecture definition, RTL design, co-work with verification owner

n Experience on video/DMA/CPU IP design and verification

Requirements:

have:

n BSEE Degree or above

n 3 or 5 years of experience in ASIC design

n Familiar with industry synthesis/STA/formal/LP/DFT tools

n Familiar with at least one of script language such as perl/tcl/shell

n Solid RTL design experience, better in video/DMA/CPU system

n Self-motivated in solving problems

n Good communication skills and fluent in English.

n Good team player.

产品经理/主管
职位描述:

基本职责：
1． 负责产品的定义和市场推广
2． 负责和工程团队的日常沟通以及和客户的交流工作。

要求：
1． 熟悉IP core领域的产品定义，对该领域的主要公司和产品有深入的了解和研究。
2． 具备一定的市场推广经验。
3． 熟悉多媒体音视频领域(如H.264, H.265的算法、标准及相关概念。
4． 对数字图像处理，数字视频处理有一定的了解。
5． 熟悉IP 设计领域的流程，具备FPGA，芯片设计相关知识。
6． 电子工程，计算机硬件等相关专业，五年以上工作经验。
7． 出色的协调能力和沟通能力，英文流利。

ASIC Design IP Core H.264 MPEG
职位职能: 硬件工程师
职位描述:

Position Description:
The video architect will be working closely with the algorithm team and design team for development of next generation video codec IP, the responsibility includes::
1.Work with algorithm team to develop the C Model for video decoder/encoder of H.265/HEVC;
2.Work with design team for the micro-architecture definition of video codec IP for H.265/HEVC;
3.Develop video testing framework for Video codec IP performance evaluation, analysis and tuning;

Qualification:
4.BS with 5+ years or MS/Ph.D with 2+ years experiences in electronic engineering/computer science;
5.Proactive, creative and team player;
6.Proficient in video and image processing techniques, in-depth understanding of algorithm and implementation for video coding standards such as MPEG-2, MPEG-4, H.263, H.264/AVC;
7.Proven related engineering experiences in architecture/micro-architecture definition for video codec development with successful tape-outs/production;
8.Solid programming skills with C/C++;
9.Knowledge/experiences of computer architecture is a plus;

1. 负责带领设计团队将视频，图像处理和编解码算法在FPGA上高效实现；
2. 负责相关IP core的后端设计的技术支持；
3. 技术团队的组织和日常管理

岗位要求：
1. 电子、微电子或相关专业，5年以上集成电路设计工作经验；
2. 精通数字集成电路设计编程语言verilog；
3. 熟悉数字前端IC设计流程；
4. 熟练使用Cadence, Synopsys等相关的EDA设计工具；
5. 熟悉视频编解码的技术标准
6. 良好的中英文表达能力和交流能力.

软件工程师 系统架构设计师
职位描述:

从事多媒体算法的设计、实现和优化工作。

任职要求：
1、 计算机或相关专业，硕士（或优秀本科），CET-6，精通C/C++；
2、 熟悉开发相关知识，良好的数学背景；
3、 符合以下条件者优先考虑：
1) 熟悉OpenCV使用及算法原理
2) 熟悉图像处理的基本问题和常见算法；
3) 熟悉计算机视觉与模式识别算法研究和应用
4) 熟悉汇编、ARM、DSP（TI、ADI等）优化 或 MMX/SSE/SSE2/SSE4及Intel/AMD的体系架构级的程序优化。

软件工程师 网络工程师
职位描述:

1、精通C/C++语言；
2、精通TCP/IP协议；
3、熟悉SIP/RTSP/RTP等网络协议，了解NAT及防火墙穿越；
4、熟悉linux编程者优先；
5、硕士以上学历，计算机，电子工程相关专业；
6、工作踏实，有责任心，具有良好的团队合作精神。

ASIC Design IP Core H.264 MPEG
职位职能: 高级硬件工程师
职位描述:

Position Description:
The candidate will be the part of the design team for the development of next generation of video codec IP, the responsibilities include:
1.Micro-architecture definition;
2.Logic implementation with Verilog HDL;
3.Block-level verification;
4.Synthesis and pre-layout/post-layout timing closure;
5.Power analysis and reduction;
6.FPGA prototyping and debugging;

Qualification:
7.BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;
8.Expect elf-motivation and team player;
9.Solid skills and rich experiences in logic design, synthesis and timing analysis;
10.Hands-on engineering experiences in video codec development, familiar with video coding standard such like H.264/AVC, MPEG-4, AVS etc.;
11.Familiar with all front-end flows including LINT check, simulation, synthesis, STA, formal and power analysis, etc.;
12.Knowledge and experiences in Computer Architecture and RISC processor (ARM/MIPS/SPARC) micro-architecture would be a great plus;
13.Familiar with AXI4/AXI3 protocol, memory controller would be a plus;
14.Experience in FPGA prototyping and debugging would be a plush;

负责或参与图像处理算法的研究并负责图像处理算法的编码实现。

任职要求：
1、硕士及以上学历，图像处理、计算机视觉、模式识别相关专业研究方向；
2、2年以上相关工作经验；
3、精通C/C ；
4、有图像处理和增强方面的独立研发能力及项目经验；
5、有成功的图像处理和计算机视觉项目，或发表过相关学术论文/专利者优先；
6、良好的沟通能力及团队合作精神。

1.
从事模式识别/机器学习等方向的算法研究


2.
从事图像处理和视频分析相关领域研究和开发



3.
从事模式识别相关产品开发






职位要求：
1.
精通模式识别、机器学习、数据挖掘等一个或多个方向
2.
具有图像处理或视频分析基础知识
3.
有人脸识别，文字识别经验者更佳
4.
计算机、电子、自动化、数学等相关专业，硕士以上学历

CAD EDA ASIC
职位职能: 硬件工程师
职位描述:

Position Description:
The candidate will be working IT/CAD related technical support including UNIX environment and EDA tools. The responsibilities include:
1.Administer and support computer/server systems and associated equipment, install, configure, and maintain hardware/software;
2.Support development team for automated CAD environment, set up and maintain the design flow for front-end ASIC development;
3.Work with AEs of EDA vendors to resolve EDA related issues;

Qualification:
4.BS or above with 3+ years experiences in electronic engineering/computer science;
5.Outstanding problem resolving skills, result-driven and highly motivated in the pursuit of solutions to challenging technical problems; good communication skills;
6.Experiences in UNIX and EDA tools support;
7.Familiar with UNIX Operating Environment;
8.Familiar with commonly used EDA tools for front-end ASIC design/verification, knowledge of ASIC design methodology and flows, programming skills with Perl/Tcl is required;

Senior ASIC design Engineer 集成电路IC设计/应用工程师
职位描述:

Responsibilities:
？ IP level micro-architecture, RTL design, verification, synthesis
？ SOC integration including chip level clock/reset structure, low power implementation, synthesis, low power verification and timing closure
？ Participating in company’s engineering update such as methodology improvement, new technology study and evaluation
？ Coordinating joint development with 3rd party:
？ IP selection/management and vendor coordination
？ Interface with 3rd party vendor for successful execution
Requirements:
Must have:
？ BSEE Degree or equivalent
？ 3-5 years of experience in hands-on IC design
？ Familiar with ASIC design methodology and SOC architecture.
？ Familiar with standard EDA tools of simulation, synthesis, low power, formal, STA
？ Self-motivated in solving problems
？ Good communication skills and fluent in English.
？ Good team player.

A plus to have:
？ Good scripting skills.
？ Low power design experience
？ Video/DMA design experience.
？ Experience in DFT
DSP Algorithm Engineer
Job Response:
Collection use cases of chip, and analyze use cases' requirement on chip and each IP
Design and optimize chip or IP architecture based on power, die size and performance requirement for different use cases with proper document
Use c model to modeling critical behavior of chip, such as power consumption, data traffic and control traffic between IP
Cooperate with IC team, software team and system team to implement chip, verification chip and validate chip
Hands-on RTL coding and verification of critical blocks.

Qualifications:
Proficiency in develop high speed / low power circuits with good knowledge of RTL / synthesis / backend.
Proficiency in architecture design and implementation of high speed / low power IP or Chip
Experience on c/c++ program or modeling
Good knowledge of SOC design.
Experience video processing or signal processing
Self-motivated and good team player,
Good communication skills and fluent in English.?
MSEE with 4+ years or BSEE with 6+ years.
Senior Software Engineer
Job description:
We are seeking for a staff Software Engineer with good experience in video processing software development on embedded system. In this position, you will be involved in the core technology design and development for SOC (System-on-Chip) Product. You will be responsible for designing and developing video/audio/Network/USB drivers on SOC, and developing applications.

Requirements:
Good understanding of Linux programming and architecture
Strong C and/or C++ and ASM* design, coding and debugging expertise
Be proficient in Linux driver development
Be proficient in embedded video and image process
Be proficient in embedded network function development
English read and write ability
5+ years experience with embedded programming
Be experienced in 8051 chip.

As a DSP (Digital Signal Processing) engineer for Pixelworks, the candidate will join a team of experienced scientists and engineers to develop exciting technology in image and video processing. The position will give you an opportunity to combine your ingenuity with the next generation products in TV and Panel industry. Typical duties performed as follow:
1. Design and implementation of video post processing algorithm such as true motion based frame interpolation, super-resolution, noise reduction;
2. Design and implementation of image algorithm such as local dimming, scaling, color enhancement and deinterlacing;
3. Support the verification and optimization of algorithm according to HW requirements;
4. Work with image quality team to improve image quality, and tune image quality according to requirements of customers.


Requirements
1. Ph. D in EE/CS specializing in digital signal processing, image processing, video processing, computer vision, pattern recognition, or computer graphics;
2. Thorough background in signal processing, image and video processing, statistical analysis and pattern recognition;
3. Proven ability in designing, implementing, debugging and understanding complex algorithm;
4. Solid programming skills in C/C++ and MATLAB;
5. Strong analytical, creative, self-motivated, good communications skill;
6. Enjoy R&D work, open and positive attitude;
7. Strong communication skills, presentation skills, good organization and skilled in writing high quality engineering documentation.


Additional Preferred Skills
8. Experience with IC design flow and methodologies; experiences with algorithm design targeted for IC and FPGA;
9. Previously worked on video processing algorithms such as motion estimation, super resolution, deinterlacing, scaling, noise reduction is a big plus;
10. Familiar with digital video algorithm and interfaces;


嵌入式硬件开发(主板机…)
职位描述:

KEY RESPONSIBILITIES
Work at system level of USB, Ethernet, SD/MMC interface
Study industry standard document and IP specification
Understand the theory of operation of those interfaces
Be familiar with those interface protocol
Be familiar with registers inside those IP
Be familiar with the electrical specification of those interface
FPGA verification and Silicon validation
Able to create checklist based on the understanding of those IPs
Run test case based on created checklist
Support IC/SW team for debug
Create validation report
Create product datasheet
Create registers description
Create the theory of operation
Customer support
Solve issues from FAE or customers
Answer questions from FAE or customers.


REQUIREMENTS
B.Sc. or M.Sc. In Electrical engineering or equivalent is required
At least 3 years experience in PC, Consumer or communication electronics product development
Able to communication in English.


Optional requirement
Develop or application experience with USB, Ethernet or SD/MMC interface.
Previous Hands on high speed board design experience for an ASIC company
Previous Hands on DDR2, DDR3, Denali controller, USB2, HDMI, Ethernet for high speed application
Knowledge of analog and digital designs
Knowledge of video standards and television standards an asset
Knowledge of product compliance and safety requirements
Program management experience


嵌入式软件开发(Linux/单片机/DLC/DSP…) 高级软件工程师
职位描述:

Job description:We are seeking for a staff Software Engineer with good experience in video processing software development on embedded system. In this position, you will be involved in the core technology design and development for SOC (System-on-Chip) Product. You will be responsible for designing and developing video/audio/Network/USB drivers on SOC, and developing applications. Requirements:1. Good understanding of Linux programming and architecture2. Strong C and/or C++ and ASM* design, coding and debugging expertise3. Be proficient in Linux driver development4. Be proficient in embedded video and image process5. Be proficient in embedded network function development6. English read and write ability7. 5+ years experience with windows programming 8. USB experience
IC验证工程师
职位描述:

We are looking for Sr. Verification engineer with systemC/systemVerilog back ground. Past experience in video processing SOC verification is a plus.

Responsibilities:
Responsibilities will include developing verification environment; developing test plans for and verifying the function of ASIC; hands-on implementation work for every aspect of ASIC verification, working closely with the system group, architects, design and verification teams. The successful candidate should have experience going through at least one complete and successful ASIC design/verification cycle from architecting and creating ASIC test environment to full completion of the verification work. The candidate also needs to have a full understanding of design using Verilog and working experience with Systemverilog. A strong communication skill in both Chinese and English is required.

Qualifications:
4+ years of ASIC verification experience, complex SOC verification experence is preferred
good programming skills in C/C++
Knowledgeable in OVM or VMM, UVM is perferred
Responsible for implementation of verification environment and generation of high quality test cases.
BS/MS EE, CE or CS
集成电路IC设计/应用工程师
职位描述:

Description of Duties and Responsibilities:
1. Proficiency in whole Chip DFT architecture definition and DFT plan review;
2. Be responsible for defining/Implementing different schemes of DFT aspects: including scan insertion, ATPG generation, MBIST insertion, Boundary scan and functional test pattern generation; (Mentor DFT flow is a plus)
3. Be responsible for DFT related STA; work with BE, analog team and third party to drive full chip P&R and timing closure.
4. Experience with pre and post RTL/netlist simulation, good debug capability; familiar with Verilog;


Preferred Experience:
1. ATE on-line debugging background is a plus;
2. Experience with 65nm or 45nm process is a plus; and/or several chip sign-off;
3. Setup and maintain DFT related flow;
4. Familiar with logic synthesis, Formal Verification flow;
5. Strong problem solving skills; self-motivated and good team player; can take international business trip if needed.




(Senior) Engineer, Analog Mixed Signal Design

职位描述:

Responsibilities:
Main job duty will be CMOS analog mixed signal design, which includes specification definition, architectural exploration, modeling, schematic design, and pre/post-layout simulation. Successful candidate will report to the head of the Analog Mixed Signal Design team

Requirements:
Experience on CMOS deep submicron process is a must; knowledge in 65nm and below will be good.
Experience with the following analog IP will be a plus,
Gigabit Serdes design
Analog/Digital Phase Lock Loop, DLL design
HDMI, SATA, DisplayPort, and PCIe PHY design
Familiar with IP bench characterization and ATE test.
EDA tools: Cadence customer analog design flow; Mentor physical verification flow
Master's degree. doctor's degree is preferred.
5 years or more work experience in relevant industry
Candidate with the right experience and design skills will be considered for the Staff engineering level posting

















信息技术专员
职位描述:

Responsibilities:
? Provides day-to-day technical support to employees for internal desktop systems software and hardware.
? Installs, configures and troubleshoots desktop systems, workstations, and network connectivity issues.
? User and group administration.
? Communicates highly technical information to both technical and non-technical personnel.
? Provide periodic scheduled after hours phone support to the employee populace.
? Recommends hardware and software solutions, including new acquisitions and upgrades.
? Research into new desktop (client/server) software tools and utilities。

Requirements:
? 5+ years of experience working in a windows domain environment
? Must work well within a team and possess strong written and oral communication skills
? Must be able to operate independently in the absence of strict guidance to correct issues and improve the environment
? Must possess strong problem solving and troubleshooting skills in enterprise level environments, being able to logically step through issues and troubleshoot problems by thinking outside of the box and being creative with your solutions
? Must be able to relate technical issues and requirements to business issues and vice versa and be able to communicate these to non-technical associates and customers

Desired:
? Associate’s Degree plus 2 year’s experience in a Client/Server environment.
? Knowledge with Windows 2008, Windows 7, Office 2007/2010 and a variety of desktop software tools including Anti-virus, Anti-SPAM, Anti-Spyware, asset tracking , remote connectivity (VPN)
? Knowledge of Software license audit.
? Knowledge of Mailserver and OS deploy.
? Experience with LAN admin and IP-phone

云计算（广义协同计算） 职位

（1）公司核心算法的多核（移动终端和云）服务研发工作；
（2）搭建多核（移动终端和云）架构，提供面向各平台的云计算和服务。
（3）高性能的服务端开发工作；

（1）进行业务系统数据库的规划、设计、实施，设计并优化数据库物理建设方案；
（2）对数据库进行管理，负责数据库应用系统的运营及监控
（3）各系统数据库管理、性能调优、故障诊断、容灾处理；
（4）对系统数据进行挖掘、分析和报表；

任职资格
计算
1、编程能力
（1）熟悉Linux/Unix平台上的C/C++ 或PHP编程，熟悉脚本编程
（2）对Hadoop有较深入的研究与应用.
（3）熟悉GPU优化最好
（4）熟悉多核优化最好
（5）熟悉SQL编程最好；
（6）熟悉Java最好；
（7）熟悉Js，ajax，json等相关类库或开发特点最好；

2、熟悉常用算法和数据结构，熟悉网络编程、多线程编程技术
3、熟悉数据库架构和特点，有较强的存储设计能力；

存储
1、编程能力
（1）熟悉Oracle或Sql Server数据库架构，原理及其脚本编程；
（2）熟悉NoSQL数据库结构及其特点最好；
（3）具备各类数据库系统的日常维护与管理最好；
（4）熟悉PostgreSQL特点及其开发最好；
2、熟悉数据结构，了解网络编程、多线程编程技术
3、熟悉现有各类型数据库，有较强的存储设计与开发能力；
优先考虑：
1、知名网络公司云计算、云服务、云存储相关事业部经验；
2、大型网络服务项目的分析与设计经验；

urgent position to be fulfilled is a ASIC design verification engineer. It needs experiences in CPU design. The JD is as below.



(Sr.) ASIC Design Verification Engineer



Position Description:

As part of the IP design team, the candidate will be responsible for the pre-silicon verification of in-house designed micro-processor which is a built-in component for next generation video codec IP, including:

· Build up and maintain verification environment, including development of testbench and test generators for block-level and full-chip level simulation;

· Develop and execute functional verification test plans, include writing tests, developing behavioral checkers and coverage/code monitors; Analyze coverage gaps and devise strategies to fill coverage holes;

· Work with designers to debug failing tests and resolve bugs;

· Help develop and maintain flows/scripts/tools for front-end design/verification;



Qualification:

· BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;

· Self-motivated team player, with strong problem resolving skills;

· Proficient and experienced in high-level verification methodology (VMM/UVM/OVM), Verilog-HDL, and hardware verification language (SystemC/SystemVerilog);

· Familiar with video coding standard, and/or computer architecture/micro-architecture;

· Hands-on experienced in CPU verification, including test plan and test bench development, test case development and test coverage assessment would be a great plus;

· Experiences in assembly programming, and using scripting languages (Perl/Tcl/Bash/Csh) for flow automation;

· Familiar with front-end ASIC design flow;





Position: Sr. ASIC Engineer



1. This candidate should have mobile/high speed interface background and should be interesting in R&D on Video related technologies.

2. IC/IP background. Be interesting in developing and improving New IP.

3. Integration experience, be able to own testchip tapeout.

4. With at least 3-years IP/Product R&D experience.



Job Description

- RTL coding, new logic design, simulation, synthesis.

- Work closely with algorithm engineer to develop/debug new IP/product. Supports FPGA engineer debugging issues on FPGA system.

- Work closely with system/SW engineer to verificate/validate new IP/product on FPGA/System platform.

- Deliver design/verification/application documents.

Qualification and Experience

- Very familiar with the Verilog HDL language;

- Create the RTL architecture for the algorithm;

- Very familiar with C and C++;

- Familiar with FPGA tool, ModelSim, and Synplify.

- Familiar with the flow of the IC design.



Requirements:

- Bachelor/Master degree in electronic/computer engineering

- Demonstrated abilities in working independently

- Strong communication skills




Position: ASIC Engineer of SOC and Video system


Requirements

1. BS or above in microelectronics, electrical engineering or equivalence
2. 3~5 year experience of ASIC EDA tool and front-end design/coding. Video chip experience is preferred.
3. Must have one of following EDA tool experience
a) STA, low power, DFT, synthesis
4. Must have one of following design/coding experience, video related is preferred
a) IP level micro-architecture definition, RTL design, co-work with verification owner
5. Nice to have experience of chip level clock/reset structure definition, low power partition definition
6. Good team work and communication skill (both in Chinese and English).

Responsibility

The candidate will be working on one of following items
1. SOC architecture definition and coordination including clock/reset structure definition, low power partition definition, etc.
2. Full chip timing closure, work closely with backend for tape out sign off
3. Define UPF/CPF, verify low power structure base on RTL or NETLIST level
4. Understand DFT/synthesis flow, provide necessary support
5. Video or processor related IP level micro-architecture definition, RTL design, co-work with verification owner

       上海中科睿射电子科技有限公司是一家依托中国科学院上海高等研究院，由中科院上海高等研究院和风险投资机构共同投资的高科技企业。
       中科睿射专注于移动无线通信射频前端芯片、模块的设计和制造。我们的技术源于美国硅谷，研发团队由国际知名的无线射频集成电路设计专家领衔创建，汇聚了多位各属专长的博士、硕士组成。技术方面在经过属于自己知识产权的发明创造而提升到新的高度。
       目前公司的产品有无线终端的射频功率放大器（RF PA）、低噪声放大器（LNA）、开关（Switch）以及各种射频前端组件（FEM），它们应用于Wifi、Wimax、TD-LTE、CDMA、Zigbee、Bluetooth和GSM等平台，具广阔的应用前景和市场潜力。