上海招聘

Responsibilities:

• Development of Methodology for Architectural Level Bench Marking for High Performance and Low Power Products
• Development will require validating the Quality of Results for System or IP from front-end to back-end of Lattice tool flow
• Work with silicon design on validating Bench Marking Specs and test results
• Work with the cross functional teams to develop Bench Marking Platform and Test Benches

Qualifications:

• Master degree in engineering
• Ability to successfully manage System or IP level development of Bench Marking Platform
• Logic Verification (VMM/System Verilog is a plus)
• 5+ years’ experience in developing RTL for Embedded Processor System level designs
• Strong Working Knowledge of RTL Verilog/VHDL coding, RTL Compiler, scripting, C or C++ programming
• Experience working with simulation tools VCS, ModelSim, Verilog XL
• Experience in both RTL and gate level verification and debug
  Experience in coverage based/random test environment and assertion generation
• Demonstrable knowledge of successful testing strategies and testbench architectures
• Knowledge of High Speed transceiver technologies a plus
• Strong communication skills
• Willingness to work with teams in US, Philippines and India
• Highly organized, with attention to details, time management, and deadlines
  Ability to multi-task and set priorities in a fast-paced environment
• Knowledge of Communications Systems would be a plus

莱迪思半导体公司是从事世界上最先进的超大规模可编程逻辑器件及相应的EDA软件系统的研究、设计、开发、生产的专业公司之一，是在系统可编程技术（In System Programmability，简称ISP）及器件的发明者和供应商，是世界上三大可编程逻辑器件供应商之一。

莱迪思半导体公司提供业界***范围的可编程逻辑器件（PLD），包括：现场可编程门列阵（FPGA）、复杂的可编程逻辑器件（CPLD）、混合信号电源管理器、时钟发生器件。莱迪思还提供业界领先的SERDES产品。

莱迪思不断地以针对系统设计的全方位的解决方案来为其客户提供最多最棒的东西，包括无以伦比的高性能、非易失、低成本的FPGA产品线。

莱迪思通过一个分布广泛的独立销售代理和分销商网络，把产品销往全世界，其产品主要针对通讯、计算机、工业、消费品、汽车、医疗和军事领域终端市场的OEM客户。

上海莱迪思半导体有限公司是美国莱迪思半导体公司于1993年6月经中国政府批准在上海独资建立的设计开发中心，拥有世界一流的设备和工作环境。公司员工大多数具有硕士以上学位或高级职称。公司主要从事世界一流FPGA、CPLD器件及相应电子设计自动化软件（EDA Software）的设计开发，并向中国大陆以及亚洲其他国家与地区的莱迪思用户提供技术应用支持、培训和咨询服务。