上海招聘

urgent position to be fulfilled is a ASIC design verification engineer. It needs experiences in CPU design. The JD is as below.


(Sr.) ASIC Design Verification Engineer



Position Description:

As part of the IP design team, the candidate will be responsible for the pre-silicon verification of in-house designed micro-processor which is a built-in component for next generation video codec IP, including:

· Build up and maintain verification environment, including development of testbench and test generators for block-level and full-chip level simulation;

· Develop and execute functional verification test plans, include writing tests, developing behavioral checkers and coverage/code monitors; Analyze coverage gaps and devise strategies to fill coverage holes;

· Work with designers to debug failing tests and resolve bugs;

· Help develop and maintain flows/scripts/tools for front-end design/verification;



Qualification:

· BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;

· Self-motivated team player, with strong problem resolving skills;

· Proficient and experienced in high-level verification methodology (VMM/UVM/OVM), Verilog-HDL, and hardware verification language (SystemC/SystemVerilog);

· Familiar with video coding standard, and/or computer architecture/micro-architecture;

· Hands-on experienced in CPU verification, including test plan and test bench development, test case development and test coverage assessment would be a great plus;

· Experiences in assembly programming, and using scripting languages (Perl/Tcl/Bash/Csh) for flow automation;

· Familiar with front-end ASIC design flow;





Position: Sr. ASIC Engineer



1. This candidate should have mobile/high speed interface background and should be interesting in R&D on Video related technologies.

2. IC/IP background. Be interesting in developing and improving New IP.

3. Integration experience, be able to own testchip tapeout.

4. With at least 3-years IP/Product R&D experience.



Job Description

- RTL coding, new logic design, simulation, synthesis.

- Work closely with algorithm engineer to develop/debug new IP/product. Supports FPGA engineer debugging issues on FPGA system.

- Work closely with system/SW engineer to verificate/validate new IP/product on FPGA/System platform.

- Deliver design/verification/application documents.

Qualification and Experience

- Very familiar with the Verilog HDL language;

- Create the RTL architecture for the algorithm;

- Very familiar with C and C++;

- Familiar with FPGA tool, ModelSim, and Synplify.

- Familiar with the flow of the IC design.



Requirements:

- Bachelor/Master degree in electronic/computer engineering

- Demonstrated abilities in working independently

- Strong communication skills




Position: ASIC Engineer of SOC and Video system


Requirements

1. BS or above in microelectronics, electrical engineering or equivalence
2. 3~5 year experience of ASIC EDA tool and front-end design/coding. Video chip experience is preferred.
3. Must have one of following EDA tool experience
a) STA, low power, DFT, synthesis
4. Must have one of following design/coding experience, video related is preferred
a) IP level micro-architecture definition, RTL design, co-work with verification owner
5. Nice to have experience of chip level clock/reset structure definition, low power partition definition
6. Good team work and communication skill (both in Chinese and English).

Responsibility

The candidate will be working on one of following items
1. SOC architecture definition and coordination including clock/reset structure definition, low power partition definition, etc.
2. Full chip timing closure, work closely with backend for tape out sign off
3. Define UPF/CPF, verify low power structure base on RTL or NETLIST level
4. Understand DFT/synthesis flow, provide necessary support
5. Video or processor related IP level micro-architecture definition, RTL design, co-work with verification owner

简历发jinjuan@raiserf.com

       上海中科睿射电子科技有限公司是一家依托中国科学院上海高等研究院，由中科院上海高等研究院和风险投资机构共同投资的高科技企业。
       中科睿射专注于移动无线通信射频前端芯片、模块的设计和制造。我们的技术源于美国硅谷，研发团队由国际知名的无线射频集成电路设计专家领衔创建，汇聚了多位各属专长的博士、硕士组成。技术方面在经过属于自己知识产权的发明创造而提升到新的高度。
       目前公司的产品有无线终端的射频功率放大器（RF PA）、低噪声放大器（LNA）、开关（Switch）以及各种射频前端组件（FEM），它们应用于Wifi、Wimax、TD-LTE、CDMA、Zigbee、Bluetooth和GSM等平台，具广阔的应用前景和市场潜力。