上海招聘

射频工程师
职位描述:

1. 重点大学博士毕业三年工作以 上经验或硕士毕业五年工作以上经验；
2. 扎实的射频、微波电路理论知识及相关的电路设计经验。
3. 熟悉高频元器件，从事过GaAs 或CMOS Power amplifier， LNA， mixer（up-converter and down-converter），filter，antenna，等方面的设计工作，有相关3G/4G线性功放经验者为佳。
4。具有 MMIC,RFIC，功率放大器线性化技术之一者为佳。
5. 对无线通信数字调制和解调有一定的了解， 有一定的半导体技术基础；
6. 熟悉ADS、HFSS、Cadence等EDA设计软件，及主要射频及微波测试仪器的使用。
7. 具有成功量产经验。
8. 具有一定的领导能力。
9. 通过国家英语六级水平测试，具有较强的英文表达与沟通能力。工作认真、积极负责，并具有优良的团队合作意识

CMOS
职位职能: 集成电路IC设计/应用工程师
职位描述:

1. 重点大学博士毕业三年工作以 上经验或硕士毕业五年工作以上经验；
2. 扎实的模拟电路，射频理论知识及相关的电路设计经验。
3. 熟悉高频元器件，从事过CMOS Power amplifier， LNA， mixer（up-
converter and down-converter），PLL等方面的设计工作。
4. 对bandgap，DC/DC converter，LDO和chargepump等模拟电路有深入的了解。
5. 熟悉ADS、HFSS、Cadence等EDA设计软件，及主要射频及微波测试仪器的使用。
6. 具有成功量产经验。
7. 具有一定的领导能力。
8. 通过国家英语六级水平测试，具有较强的英文表达与沟通能力。工作认真、积
极负责，并具有优良的团队合作意识

CMOS研发经理

CMOS
职位职能: 集成电路IC设计/应用工程师
职位描述:

1. 重点大学博士毕业三年工作以 上经验或硕士毕业五年工作以上经验；
2. 扎实的模拟电路，射频理论知识及相关的电路设计经验。
3. 熟悉高频元器件，从事过CMOS Power amplifier， LNA， mixer（up-
converter and down-converter），PLL等方面的设计工作。
4. 对bandgap，DC/DC converter，LDO和chargepump等模拟电路有深入的了解。
5. 熟悉ADS、HFSS、Cadence等EDA设计软件，及主要射频及微波测试仪器的使用。
6. 具有成功量产经验。
7. 具有一定的领导能力。
8. 通过国家英语六级水平测试，具有较强的英文表达与沟通能力。工作认真、积
极负责，并具有优良的团队合作意识

工作职责：
1.封装、测试厂开拓与维护，与封测厂合作，在提高产品良率的同时，保证产品质量。 2.产品量产质量管理，对内质量体系的建立和执行，对外晶圆厂的Wafer和封装厂的封测进行质量管理。 3.异常品质分析调查、出货追踪等。 4.建立ISO质量体系、维护公司内部、外部文件管控程序。

工作要求：
1.本科以上学历，微电子相关专业； 2.有三年以上质量管理工作经验； 3.熟悉半导体行业质量体系，具有内审资格； 4.有晶圆厂或封测厂工作经验者优先。

Physical design Leader/staff engineer ：
这个人是要带团队的，我觉得个性很重要，而且还要自己组建团队，人脉也很重要


1. lead soc design team;
2. be able to interface &communicate with internal colleague and external customer;
3. be able to provide design guidance and instruction to engineers;
4. be able to hands-on work on Top level/block level physical design independently

JR:
1. minimum of 5 yrs of working experience;
2. master degree of EE or related field is preferred;
3. team leader or functional leader experience is preferred;
4. familiar with either Synopsys or Cadence design flow and EDA tools;
5. fluent in both Chinese and English


下面的职位要求，有其中之一最好没有也不强调：
1. Responsible for all aspects of physical design and implementation of integrated circuits and other ASIC.
2. Responsibilities include: Participating in the efforts in establishing CAD and physical design methodologies;
3. Focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology);
4, Chip floor plan; Power/clock distribution;
5. Chip assembly and P&R; Timing closure;
6. Power and noise analysis;
7. Back-end verification across multiple projects;


Requirements:
1. BSEE 5+years,MSEE 3+years experience in large VLSI physical design implementation;
2. Successful track record of delivering products to production is a must;
3. Understanding of custom Macro blocks such as RAMs, PLLs, high-speed IO drivers;
4. Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues;
5. Working knowledge of deep sub-micron routing issues as they relate to power and timing;
6. Circuit level comprehension of time critical paths. Spice experience a plus;
7. Should be a power user of Apollo/Astro for routing, PhysOpt (Physical Compiler) for placement, PrimeTime for Timing Verification, dc_shell etc.


PR Engneer


Responsibilities:
1. Layout database creation : layout library and Milkyway database creation;
2. Initial floorplan : Initial chip or subchip level floorplan;
3. Place & Route: Perform cells placement; Perform global route and detail route;
4. DRC/LVS corrections; Layout script creation: Create script to perform layout modification;
5. Create Apollo scheme file to maintain and update Apollo database;
6. Layout modification: Follow signal integration report to perform necessary modification;
7. Requirements: Bachelor Degree or higher in EE major;
8. 0-3 years P&R working experience;
9. Knowledge about Solaris/Unix/Linux operating system; Good command of English in both written and oral format.


DFT Engineer
1. Responsibilities: Synthesis: Use DC (Design Compiler), ACS (Advanced Chip Synthesis), and PC (Physical Compiler) for chip synthesis either from RTL code or Gate level netlist;


2. Static Timing analysis and Formal verification: Perform timing analysis and timing optimization;
3. Run formal verification after each ECO and timing optimization;


4. DFT design: Scan chain insertion; JTAG/Boundary scan insertion; NAND tree insertion;


5. Memory BIST insertion; Logic BIST insertion;
6. Test pattern generation and simulation: ATPG test vector generation and pattern simulation;
7. Fault grading test vector generation;
8. Memory BIST simulation; JTAG/NAND tree simulation;
9. Test vectorl format conversion and provide all test related patterns to test and product engineers;
10. Requirements: BS, MS preferred; 0-3 years working experience on chip integration;
11. Strong Logic design and Semiconductor device physic background; Good English in both written and spoken.

数字后端经理 Physical design manager、Leader/staff engineer ：
这个是带团队的，需要技术和个人魅力都结合的职位，简历发HR@hi-talent.net


1. lead soc design team;
2. be able to interface &communicate with internal colleague and external customer;
3. be able to provide design guidance and instruction to engineers;
4. be able to hands-on work on Top level/block level physical design independently

JR:
1. minimum of 5 yrs of working experience;
2. master degree of EE or related field is preferred;
3. team leader or functional leader experience is preferred;
4. familiar with either Synopsys or Cadence design flow and EDA tools;
5. fluent in both Chinese and English


后端设计验证 经理
职位职能: 集成电路IC设计/应用工程师
职位描述:

工作地点：上海徐汇区
职责概述 :
SOC后端设计和验证
- 参与IC设计布局布线, STA等环节的环境和流程维护
- 从事后端设计从netlist到GDSii的实现
- 编写相关脚本或约束，进行布局布线，时钟树生成，物理验证，功耗/电压降分析, 寄生参数提取等
- 产生并分析运行报告并给出解决方法

专业背景要求:
- 电子工程、计算机科学或相关学科本科3年、硕士3年以上工作经验
- 熟悉IC设计流程和常识，特别是当前流行的后端设计流程
- 熟练使用下面一种或几种EDA开发工具
- 擅长IC版图规划，电源规划，布局布线，时钟树生成、DRC/LVS经验者优先；有一些定制设计和模拟IP
使用经验者优先；有功耗分析电压降分析经验者优先；有串扰和信号完整性分析经验者优先
- 有90nm或65nm或.13工艺成功流片经历


综合素质要求:
- 良好的沟通能力和团队合作精神
- 高度的责任心和敬业精神
- 较强的逻辑思维能力，善于发现问题，具有良好的自学能力和解决问题的能力
- 英语熟练应用。
-本专业优先。


下面的职位要求，有其中之一最好没有也不强调：
1. Responsible for all aspects of physical design and implementation of integrated circuits and other ASIC.
2. Responsibilities include: Participating in the efforts in establishing CAD and physical design methodologies;
3. Focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology);
4, Chip floor plan; Power/clock distribution;
5. Chip assembly and P&R; Timing closure;
6. Power and noise analysis;
7. Back-end verification across multiple projects;


Requirements:
1. BSEE 5+years,MSEE 3+years experience in large VLSI physical design implementation;
2. Successful track record of delivering products to production is a must;
3. Understanding of custom Macro blocks such as RAMs, PLLs, high-speed IO drivers;
4. Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues;
5. Working knowledge of deep sub-micron routing issues as they relate to power and timing;
6. Circuit level comprehension of time critical paths. Spice experience a plus;
7. Should be a power user of Apollo/Astro for routing, PhysOpt (Physical Compiler) for placement, PrimeTime for Timing Verification, dc_shell etc.


PR Engneer


Responsibilities:
1. Layout database creation : layout library and Milkyway database creation;
2. Initial floorplan : Initial chip or subchip level floorplan;
3. Place & Route: Perform cells placement; Perform global route and detail route;
4. DRC/LVS corrections; Layout script creation: Create script to perform layout modification;
5. Create Apollo scheme file to maintain and update Apollo database;
6. Layout modification: Follow signal integration report to perform necessary modification;
7. Requirements: Bachelor Degree or higher in EE major;
8. 0-3 years P&R working experience;
9. Knowledge about Solaris/Unix/Linux operating system; Good command of English in both written and oral format.


DFT Engineer
1. Responsibilities: Synthesis: Use DC (Design Compiler), ACS (Advanced Chip Synthesis), and PC (Physical Compiler) for chip synthesis either from RTL code or Gate level netlist;


2. Static Timing analysis and Formal verification: Perform timing analysis and timing optimization;
3. Run formal verification after each ECO and timing optimization;


4. DFT design: Scan chain insertion; JTAG/Boundary scan insertion; NAND tree insertion;


5. Memory BIST insertion; Logic BIST insertion;
6. Test pattern generation and simulation: ATPG test vector generation and pattern simulation;
7. Fault grading test vector generation;
8. Memory BIST simulation; JTAG/NAND tree simulation;
9. Test vectorl format conversion and provide all test related patterns to test and product engineers;
10. Requirements: BS, MS preferred; 0-3 years working experience on chip integration;
11. Strong Logic design and Semiconductor device physic background; Good English in both written and spoken.


简历发jinjuan@raiserf.com

       上海中科睿射电子科技有限公司是一家依托中国科学院上海高等研究院，由中科院上海高等研究院和风险投资机构共同投资的高科技企业。
       中科睿射专注于移动无线通信射频前端芯片、模块的设计和制造。我们的技术源于美国硅谷，研发团队由国际知名的无线射频集成电路设计专家领衔创建，汇聚了多位各属专长的博士、硕士组成。技术方面在经过属于自己知识产权的发明创造而提升到新的高度。
       目前公司的产品有无线终端的射频功率放大器（RF PA）、低噪声放大器（LNA）、开关（Switch）以及各种射频前端组件（FEM），它们应用于Wifi、Wimax、TD-LTE、CDMA、Zigbee、Bluetooth和GSM等平台，具广阔的应用前景和市场潜力。