上海招聘

简历发jinjuan@raiserf.com

射频，无源器件，电磁场分析
职位职能: 射频工程师 集成电路IC设计/应用工程师
职位描述:
职责：
基于硅片上的滤波器、耦合器、巴伦、功率分配器、双工器,以及片上电阻、电容和电感等射频集成无源器件设计、建模、封装、测试。
要求：
精通硅衬底上射频无源器件的集成化、小型化设计；
熟练使用电路分析软件Cadence Virtuoso和ADS，熟练使用电磁场分析软件ADS Momenturm和HFSS;
了解无线通信系统及系统对各无源器件指标要求；
熟练使用探针测试台和矢量网络分析仪进行射频芯片及封装的测试等；
熟悉IPD设计和射频芯片的flipchip和wirebond等封装形式尤佳。

Responsibility：
Design, simulate and characterize on-chip passvie components, including inductors, capacitors, filters, diplexers, and baluns for applications in wireless communication modules and other microelectronics.
Design test-fixtures for passive components at chip and package level measurement with VNA.
Work with IC foundry and packaging companies to carry out passive component design and manufacture.
Requirements:
Be familiar with circuit simulation tools such as Cadence Virtuoso and ADS
Be familiar with electromagnetic simulation tools such as ADS Momentum and HFSS
Knowledge of wireless architecture and design spec for each subsystem
Knowledge of circuit, transmission line and EM theory and RF/microwave design techniques
The experience on the IPD design with wirebond or flipchip packaging will be a plus.


另外一个职位是：深圳和上海的FAE职位

职位描述
1、WiFi模块/智能手机射频性能的调试和测试
2、协助客户进行射频电路设计
工作经验要求 沟通能力良好，适应团队合作
有以下条件者优先采纳:
- 熟悉WiFi/3G综测仪（例如，IQ2010/Aglient8960），测试方法和测试指标
- 熟悉RF PA 相关的性能指标以及相关的测试方法
专业技能要求 1、本科及以上学历，通信工程、电磁场与微波技术、电路与系统、电子工程等专业；
2、熟练掌握高频电子线路原理、具备射频电路的相关知识；
3、对现代无线通信系统有常识性了解；
4、熟练掌握电路设计软件Protel99/PAS/Candence其中一款或多款，能够独立进行射频电路原理图与PCB设计；
5、熟练操作各种射频测试设备（信号发生器，网络分析仪，频谱分析仪），能够进行射频电路的测试测量；
6、熟练使用焊接工具

数字后端经理 Physical design manager、Leader/staff engineer ：
这个是带团队的，需要技术和个人魅力都结合的职位，简历发HR@hi-talent.net


1. lead soc design team;
2. be able to interface &communicate with internal colleague and external customer;
3. be able to provide design guidance and instruction to engineers;
4. be able to hands-on work on Top level/block level physical design independently

JR:
1. minimum of 5 yrs of working experience;
2. master degree of EE or related field is preferred;
3. team leader or functional leader experience is preferred;
4. familiar with either Synopsys or Cadence design flow and EDA tools;
5. fluent in both Chinese and English


后端设计验证 经理
职位职能: 集成电路IC设计/应用工程师
职位描述:

工作地点：上海徐汇区
职责概述 :
SOC后端设计和验证
- 参与IC设计布局布线, STA等环节的环境和流程维护
- 从事后端设计从netlist到GDSii的实现
- 编写相关脚本或约束，进行布局布线，时钟树生成，物理验证，功耗/电压降分析, 寄生参数提取等
- 产生并分析运行报告并给出解决方法

专业背景要求:
- 电子工程、计算机科学或相关学科本科3年、硕士3年以上工作经验
- 熟悉IC设计流程和常识，特别是当前流行的后端设计流程
- 熟练使用下面一种或几种EDA开发工具
- 擅长IC版图规划，电源规划，布局布线，时钟树生成、DRC/LVS经验者优先；有一些定制设计和模拟IP
使用经验者优先；有功耗分析电压降分析经验者优先；有串扰和信号完整性分析经验者优先
- 有90nm或65nm或.13工艺成功流片经历


综合素质要求:
- 良好的沟通能力和团队合作精神
- 高度的责任心和敬业精神
- 较强的逻辑思维能力，善于发现问题，具有良好的自学能力和解决问题的能力
- 英语熟练应用。
-本专业优先。


下面的职位要求，有其中之一最好没有也不强调：
1. Responsible for all aspects of physical design and implementation of integrated circuits and other ASIC.
2. Responsibilities include: Participating in the efforts in establishing CAD and physical design methodologies;
3. Focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology);
4, Chip floor plan; Power/clock distribution;
5. Chip assembly and P&R; Timing closure;
6. Power and noise analysis;
7. Back-end verification across multiple projects;


Requirements:
1. BSEE 5+years,MSEE 3+years experience in large VLSI physical design implementation;
2. Successful track record of delivering products to production is a must;
3. Understanding of custom Macro blocks such as RAMs, PLLs, high-speed IO drivers;
4. Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues;
5. Working knowledge of deep sub-micron routing issues as they relate to power and timing;
6. Circuit level comprehension of time critical paths. Spice experience a plus;
7. Should be a power user of Apollo/Astro for routing, PhysOpt (Physical Compiler) for placement, PrimeTime for Timing Verification, dc_shell etc.


PR Engneer


Responsibilities:
1. Layout database creation : layout library and Milkyway database creation;
2. Initial floorplan : Initial chip or subchip level floorplan;
3. Place & Route: Perform cells placement; Perform global route and detail route;
4. DRC/LVS corrections; Layout script creation: Create script to perform layout modification;
5. Create Apollo scheme file to maintain and update Apollo database;
6. Layout modification: Follow signal integration report to perform necessary modification;
7. Requirements: Bachelor Degree or higher in EE major;
8. 0-3 years P&R working experience;
9. Knowledge about Solaris/Unix/Linux operating system; Good command of English in both written and oral format.


DFT Engineer
1. Responsibilities: Synthesis: Use DC (Design Compiler), ACS (Advanced Chip Synthesis), and PC (Physical Compiler) for chip synthesis either from RTL code or Gate level netlist;


2. Static Timing analysis and Formal verification: Perform timing analysis and timing optimization;
3. Run formal verification after each ECO and timing optimization;


4. DFT design: Scan chain insertion; JTAG/Boundary scan insertion; NAND tree insertion;


5. Memory BIST insertion; Logic BIST insertion;
6. Test pattern generation and simulation: ATPG test vector generation and pattern simulation;
7. Fault grading test vector generation;
8. Memory BIST simulation; JTAG/NAND tree simulation;
9. Test vectorl format conversion and provide all test related patterns to test and product engineers;
10. Requirements: BS, MS preferred; 0-3 years working experience on chip integration;
11. Strong Logic design and Semiconductor device physic background; Good English in both written and spoken.


简历发jinjuan@raiserf.com

       上海中科睿射电子科技有限公司是一家依托中国科学院上海高等研究院，由中科院上海高等研究院和风险投资机构共同投资的高科技企业。
       中科睿射专注于移动无线通信射频前端芯片、模块的设计和制造。我们的技术源于美国硅谷，研发团队由国际知名的无线射频集成电路设计专家领衔创建，汇聚了多位各属专长的博士、硕士组成。技术方面在经过属于自己知识产权的发明创造而提升到新的高度。
       目前公司的产品有无线终端的射频功率放大器（RF PA）、低噪声放大器（LNA）、开关（Switch）以及各种射频前端组件（FEM），它们应用于Wifi、Wimax、TD-LTE、CDMA、Zigbee、Bluetooth和GSM等平台，具广阔的应用前景和市场潜力。