上海招聘

Qualifications:
1. BS (MS preferred) in microelectronics, electrical engineering or equivalent with 3+ years of DFT design experience, preferably with large SoC chips.
2. Handy experience on scan, mbist, boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools and RTL/gate simulation.
3. RTL design and STA experience is a strong plus.
4. ATE tester experience is a plus.
5. Must be able to communicate in both written and spoken English
6. Good team work spirit and communication skill.

Description:
Sr. / Staff ASIC DFT design engineer
Focus on DFT design & debugging of leading-edge large SoC.

please send your resume to marvellphs@gmail.com

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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