上海招聘

Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create verification environment using SystemVerilog, UVM and/or C++, including reference model.
Debug tests with design engineers to deliver functionally correct design blocks.
Identify and write all types of coverage measures for stimulus and corner-cases.
Close coverage measures to identify verification holes and to show progress towards tape-out.


任职资格：
BS degree or equivalent practical experience. MS in EE or CS is preferred.
At least 1+ years of relevant experience on IP verification.
Knowledge of GFX IP is a big plus
Knowledge of classical RISC based computer architecture is a plus, like ARM, MIPS or RISC-V
Experience in the verification of designs such as CPUs, DSPs are big plus.
Experience with CPU reference modeling using C++ or SV is a big plus.
Experience with verification methodology such as UVM/OVM/VMM/SystemC/C++
Experience with SystemVerilog and SVA and Functional Coverage.
Experience of Formal Verification is a big plus.
Knowledge of and experience with industry-standard simulators, revision control systems and regression systems. Experience with the full verification life cycle and experience with functional coverage.
Good scripting skills in Python or Ruby is a plus.
Strong problem solver, communicator and team player.

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