上海招聘

Job Description:

As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

1. Deeply understand system level requirements and IP features, create sub-system design.

2. Prepare micro-architecture spec and verification plan for IP, subsystem and chip top

3. Assist with chip bring up and perform silicon functional/performance validation.

4. Assist with implementation team on netlist release, P&R suggestion and timing tuning.

Job Requirements:

1. Degree in electrical engineering, computer engineering or related technical fields

2. Good knowledge of Verilog/SystemVerilog.

3. Hand on experience on any of these tasks: Lint/CDC check, SDC/UPF generation, Synthesis, Formal

4. A high-level of self-motivation and a proactive approach to solving problems

Solid knowledge in one of the following areas is a plus:

1. Hands on experience on Subsystem level design;

2. Familiar with Vendor’s PCIE controller and Phy, both function and test mode.

3. Familiar with AMBA spec and SOC architecture.

3. Familiar with frontend ASIC design methodology/flow.

4. Experience of Low power design

5. Experience of follow IP is a strong plus: PCIE/UFS/USB/eMMC/GPU/ISP/MIPI/VPU/NPU/ DisplayPort/NoC/DDR/Ethernet/ AMBA AXI/AHB/APB/ GIC/SMMU/CoreSight

Siengine，芯擎科技，
是一家中外合资高科技公司，主要股东有亿咖通中国有限公司，安谋科技（中国）有限公司（ARM China）。亿咖通中国有限公司是吉利集团战略投资独立运营的全资子公司。
Siengine致力于为汽车产业的未来发展提供技术先进的SOC解决方案，并成为一家全球化的高科技公司。
我们在北京、上海、武汉有运营办公室。