上海招聘

Job Description:

    

As a senior member of design team, your responsibilities will be the following:

    

- Define Major function blocks Micro-architecture, Analysis System Performance & Latency

    

- Perform logic design and RTL coding to deliver max throughout with min power

    

- Work with the verification team on verification test plan development, coverage analysis, and full-chip simulation debug.

    

- Work with backend design teams to develop timing constraints, analyze timing violations and perform timing fixes.

    

- Work on FPGA or ASIC bring up system to resolve any lab issues or customer issues.

    

- Collaborate with software and systems teams to ensure a high quality end product

    

Job Requirements:

    

- Strong Verilog RTL coding skills and Familiar with ASIC Front-End implementation flow

    

- Experience in defining micro-architecture of complex SoC ASIC products

    

- Design knowledge of one or more of industry-standard bus interfaces (PCIe, Ethernet, Switch, GEPON, USB, DDR3, etc.) is a plus.

    

- Experience designing SoC system bus/interconnect is a plus

    

- Experience with multiple clock domains and asynchronous interfaces

    

- Strong problem solving and ASIC debugging skills, and attention to details

    

- Familiarity with EDA tools, including DC, Formality, PT and SpyGlass

    

- Familiarity with scripting languages such as TCL, Perl, Python

    

- Excellent written and verbal communications skills

    

- A self-motivated team player

    

- BS or MS in CS/EE with 7+ years of experience

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