上海招聘

Job Description
Work with Front-End design team and physical design team for super large-scale SoC chip physical implementation from RTL to GDS. Focus on physical design of deep sub-micron ultra large chip including block and chip level synthesis, floorplan, place and route, timing closure, physical verification, EM/IR signoff checks etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team.

Job Requirement
1. Hands on experience in super large-scale SoC chip physical design, especially experience in 7nm FinFet technology and high-speed design implementation.
2. Solid knowledge and rich experience on synthesis, floorplan, place, CTS and routing, static timing analysis, EM/IR-drop and physical verification.
3. Project experience on hierarchical flow such as top-level partition, timing budgeting, pin assignment and Power Network Planning etc
4. Expertise with Synopsys/Cadence/Mentor EDA tools
5. Familiar with Unix/Linux environment and good at scripts
6. A high-level of self-motivation and a proactive approach to solving problems.
7. Good communication skills, strong interpersonal skills and the flexibility
8. Dedicated, hardworking, and good team player

Siengine，芯擎科技，
是一家中外合资高科技公司，主要股东有亿咖通中国有限公司，安谋科技（中国）有限公司（ARM China）。亿咖通中国有限公司是吉利集团战略投资独立运营的全资子公司。
Siengine致力于为汽车产业的未来发展提供技术先进的SOC解决方案，并成为一家全球化的高科技公司。
我们在北京、上海、武汉有运营办公室。