上海 [切换城市] 上海招聘上海计算机硬件招聘上海硬件工程师招聘

ASIC Digital Design Engineer

新思科技(上海)Synopsys

  • 公司规模:500-1000人
  • 公司性质:外资(欧美)
  • 公司行业:电子技术/半导体/集成电路

职位信息

  • 发布日期:2020-12-27
  • 工作地点:上海
  • 招聘人数:若干人
  • 工作经验:本科
  • 学历要求:招若干人
  • 语言要求:不限
  • 职位月薪:20-40万/年
  • 职位类别:硬件工程师  集成电路IC设计/应用工程师

职位描述

Job TitleASIC Digital Design Engineer

Location: Shanghai


Job Description

- Seeking a highly motivated and innovative digital design engineer with strong theoretical and practical background in high-speed data - recovery circuits.

- Working as part of a highly experienced mixed-signal design team, the candidate will be involved in designing and maintaining current and next generation PCIe Gen5, USB 2/3 SERDES, SATA, 10G-KR and products.

- The position offers excellent opportunity to work with an expert team of digital and mixed signal designers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on the test-chips.

- In addition, this is a great opportunity to work with a wide suite of in-house digital design and verification tools, including VCS, Design Compiler, PrimeTime, Tetramax and so on

Job Responsibilities:

- Customer package creation and regression flow developed with Perl or TCL script.

- RTL coding of high-speed digital circuits, modeling of analog blocks.

- Writing verilog and system-verilog test-benches.

- Synthesis, Defining place and route constraints, resolving STA issues and performing gate-level simulations.

- Defining and debugging DFT structures in the designs for high DFT coverage.

- Design Flow development as the DFT OCC, boundary scan flow, Spyglass flow.

- Interacting with customer support and back-end design teams.


Job Requirements

- This position typically requires BS or MS plus at least 1-2 years of digital design experience in the industry as well as hands on experience in designing high-speed digital circuits, writing test-cases in Verilog and System Verilog, and familiarity with code quality metrics.

- Candidates must have a deep understanding of asynchronous clock crossings, DFT design methodologies, and synthesis implications of RTL. Knowledge of back-end synthesis tools DC/PT is a plus as are good organization and communication skills for interacting between different design groups and customer support teams.

- Candidates need to have the good learning ability and communication skill.

- Candidates needs to have the good script skill as Perl, TCL


公司介绍

公司信息
关于Synopsys新思科技公司(Synopsys, Inc.,纳斯达克股票市场代码:SNPS)提供各种产品和服务来加速全球电子市场中的创新。作为电子设计自动化(EDA)和半导体知识产权(IP)领域内的领导者,Synopsys的完整的、集成化的产品组合覆盖了系统级设计、 IP、设计实现、 验证、 制造、光学设计 、软件开发测试和现场可编程门阵列 (FPGA)等解决方案,可帮助设计师解决所面临的各种关键挑战。这些技术领先的解决方案可帮助Synopsys的客户建立竞争优势,既可以使***的产品快速地上市,同时降低成本和进度风险。

Synopsys一直是加速电子技术创新的中流砥柱,被广泛使用的Synopsys技术成功地设计并创造了数十亿的芯片和系统。公司的总部位于美国加利福尼州山景城(Mountain View,California),并且在北美、欧洲、日本、亚洲和印度设有约90个办公室。近年来,Synopsys先后收购了世界领先的软件开发测试验证工具厂商Coverity与主动性安全解决方案供应商Codenomicon等一系列公司,将公司的领先技术进一步拓宽到了软件质量与安全等领域。

Synopsys 不仅为员工(正式)提供有竞争力的薪资,并根据各地具体情况提供完善的福利保障。主要福利可能包括:
- 五险一金
- 补充公积金、住房津贴
- 午餐、交通津贴
- 员工补充医疗保险、双子女医疗保险、配偶医疗保险计划
- 股权激励计划
- 全面健康管理、健身活动
- 每年18-26天带薪休假

期待您加入Synopsys,请将简历发送至 jobs-china@synopsys.com (社招) / campus@synopsys.com (校招), 并请关注 Webchat (微信:Synopsys 招聘)。

更多信息, 请访问公司网站:***********************

联系方式

  • Email:jobs-china@synopsys.com
  • 公司地址:南京市江北新区研创园江淼路88号腾飞大厦A座20层