上海招聘

Job Description：

1. Responsible for SoC memory subsystem design, including Subsytem/IP level Design/Synthesis/STA/Formality check/Lint/CDC/Quality check.

2. Responsible for performance analysis and optimization on memory architecture, cooperate with other teams, such as core team, multi-media team.

3. Responsible for Subsystem/IP level verification, test case coding, coverage analysis.

4. Maintain and deliver high quality design, closely co-work integration，timing & power closure with Top Integration/P&R.

Job Requirements:

1. Hand on experience of Synthesis/Fomality/STA/LEC/SDC/UPF/Netlist quality check.

2. Familiar with front-end EDA tools and flows (DCG, PT, Conformal, Formality, Spyglass, GCA)

3. Familiar with Unix/Linux and scripts (tcl, perl, python, makefile etc.)

4. Experience/Knowledge on memory IP, such as NIC, NoC, DDR/LPDDR is a plus.

5. Experience/Knowledge on modeling technology, such as TLM/ESL is a plus.

6. Experience/Knowledge on signal integrity analysis is a plus.

7. A high-level of self-motivation and a proactive approach to solving problems.

Siengine，芯擎科技，
是一家中外合资高科技公司，主要股东有亿咖通中国有限公司，安谋科技（中国）有限公司（ARM China）。亿咖通中国有限公司是吉利集团战略投资独立运营的全资子公司。
Siengine致力于为汽车产业的未来发展提供技术先进的SOC解决方案，并成为一家全球化的高科技公司。
我们在北京、上海、武汉有运营办公室。