上海招聘

Job Description:

Responsible for all aspects of physical design and implementation (netlist->gds) of all chips of NVIDIA® (including GeForce^®/Tegra™/Tesla™/Quadro™).

Contribute to establish UDSM CAD, design methodologies and flow automation.

Working on floorplan, power/clock distribution, chip assembly, placement, routing, timing closure, STA, power/noise/SI analysis and physical verification.

Minimum Requirement:

BS/MS in Microelectronics or related;

Courses taken in IC design, or digital circuit design etc;

Knowledge of device model, processing technology, timing, noise and power in chip design;

Preferred Requirement:

Project experience in IC physical design implementation or familiar with semi-custom design flow;

Hands-on experience in EDA software from Synopsys (ICC/DC/PT/STAR-RC/ICV), Cadence (Encounter), Magma (Talus);

Familiar with Perl/Tcl/Shell/Makefile;

工作内容:
负责NVIDIA^® (英伟达™)公司所有芯片（包括GeForce®，Tegra™，Tesla™，Quadro™等系列）的物理设计及其实现的工作（Netlist->GDS）；协助超深亚微米CAD， 设计方法及设计流程自动化的建立。
致力于：

· 芯片规划及布局

· 电源/时钟分布及规划

· 布局布线

· 静态时序/功耗/噪声/信号完整性分析

· 物理验证

基本要求:

· 微电子及相关专业本科生或硕士生

· 有相关课程背景：集成电路设计或数字电路设计

· 有以下知识：器件模型，制造工艺，时序检查，功耗及噪声分析

优先条件：

· 有VLSI芯片项目经验或熟悉半定制设计流程

· 有相关EDA工具使用经验：Synopsys (ICC/DC/PT/STAR-RC/ICV)，Cadence (Encounter)， Magma (Talus)

· 具有脚本编写能力：Perl，Tcl，Shell， Makefile