上海招聘

RESPONSIBILITIES:

- Chip integration and netlist generation

- Synthesis

- Netlist quality check

- Formal Verification

- Constraints creation and validation, timing budget

- Co-work with PR engineers to implement chip partition and floorplan

- Work in conjunction with RR engineers to achieve timing closure for both partition level and full chip level

- Achieve special timing closure, such as io, test, clock etc.

- Function eco creation

- Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout)

- Flow automation development

- Methodology in any of above areas.

MINIMUM REQUIREMENTS:
- BSEE, MSEE is preferred

- Project experience in IC design implementation

- Courses taken in circuit design, digital design

- Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (LEC) preferred

- Proficient user of Perl or TCL is preferred

- Excellent English communication skill

工作内容:

- 芯片集成，逻辑等价性验证

- 综合，网表质量分析

- 约束文件的创建和验证，产生底层模块时序约束

- 芯片物理实现模块划分

- 芯片级和模块级时序分析和时序收敛

- 特殊电路的时序分析和时序收敛， 如IO，TEST， CLOCK等

- 产生功能ECO脚本

- 时序收敛流程的开发，维护和增强

- 流程自动化的开发

- 以上领域方法学的研究

任职需求:

-电子工程或相关专业硕士生或本科生

-有芯片设计经验

-有相关课程背景：电路设计，数字电路

-有相关EDA工具使用经验：Synopsys (DC/PT/Formality), Cadence (LEC)

-具有脚本编写能力者优先：Perl， TCL

-良好的英语交流能力