上海招聘

Job description:

Design for Testability (DFT) has become a big challenge to VLSI and SOC design as a result of the unprecedented levels of design complexity and advanced manufacturing technologies. Effective and high quality testing is extremely important for IC products especially the high end products. DFT is a must to guarantee high quality of testing hence high quality and reliability of IC products. Moreover, DFT is a significant method to reduce test cost. Nowadays, DFT is also required to provide useful means for debug and diagnosis at chip/board/system level, which is Design for Debug and Diagnosis (DFD).

As a DFT engineer at NVIDIA, you'll be responsible for cutting edge DFT involving designing key DFT logic modules and verifying them. These include test mode controllers, IO bist, Memory Bist/Repair and Jtag. In addition you will be responsible for scan insertion，ATPG post silicon validation.

We are looking for candidates of DFT Engineer who will be

- Responsible for DFT feature implementation and verification

- Developing testbench and test procedures/scripts

- Verifying Clock, Analog, JTAG, Boundary Scan, MBIST, Scan/ATPG, etc.

- Generating test vectors and doing post silicon validation

- Improving dft implementation and verification flow

Requirements:

- MSEE

- Strong logic design and verification background

- Possess basic knowledge of DFT (Scan/ATPG, MBIST, JTAG, etc.)

- Skilled in Perl/tcl programming

- Proficient at Verilog HDL

- Prefer to have experience with logic simulators and debug tools (such as vcs, ncsim, verdi)

- Familiar with C/C++, Makefile is a plus

- Strong problem solving and analytical skills

- Excellent communication skills and teamwork

随着IC设计复杂度的空前增加和制造工艺的发展，可测性设计（DFT）逐渐成为芯片设计面临的巨大挑战。有效的高质量测试对芯片产品尤其是高端芯片产品变得越加重要。DFT技术是保证芯片高质量和高可靠性的必然选择，也是降低测试成本最重要的方法。此外，DFT技术也可以为芯片级，板级和系统级的调试（Design for Debug and Diagnosis）和验证提供有效途径和方法。

作为一个NVIDIA的DFT 工程师， 你所从事的将是第一流的DFT工作 。你会有机会设计和验证DFT的关键逻辑模块（测试模块控制，IOBIST， MBIST 和 JTAG）。此外， 你还可以接触到SCAN的插入，ATPG和流片后的测试工作

工作职责：

- 负责相关DFT结构的实现和验证

- 完成相关的测试平台和测试脚本

- 完成对Clock, Analog, Jtag, Boundary Scan, MBIST, Scan/ATPG等相关部分的验证

- 负责产生测试向量并完成流片后的测试工作

- 优化DFT设计和验证流程

职位要求：

- 硕士研究生学历

- 具有熟练的数字逻辑设计和验证背景

- 精通Tcl和Perl 脚本语言

- 能够熟练运用Verilog HDL语言进行数字逻辑设计

- 熟悉IC设计和调试工具（例如VCS, nvsim ,verdi等）

- 熟悉C/C++程序设计语言设计

- 具有较强的分析问题和解决问题的能力

- 优秀的沟通和合作能力