上海招聘

Job Purpose:

Implement Design for Test strategy from the component level, ASIC level, and all the way to system level. Be responsible for component and system level DFT sign off. Participate in driving new DFT methodology and solutions to improve quality of the hardware reliability and in system test and debug capability.

Major Responsibilities:
1、Develop high-coverage DFT scheme, DFT methodology and manufacturing test flow.
2、Implement, verify and validate DFT logic.
3、Generate, verify and validate ATPG patterns for stuck-at, delay, bridging and iddq faults.
4、Write test vectors for ATE, verify, and convert them into tester format.
5、Participate in testing and debugging silicon.
6、Generate and maintain relevant design and user documentation.
7、Implement module in RTL using Verilog and assertions.
8、Assist in developing floor plans and performing full chip integration including 3rd party IPs and memory modules.
9、Work with physical design teams for optimizing layout and achieving timing closure on ASIC designs.

Job Requirement:

1、Minimum BS in EE, MSEE degree preferred with 5+ years of experience in chip design
2、Must have very strong background in DFT, BIST, JTAG/BS and ATPG.
3、Must have extensive hands-on experience with either Mentor DftAdvisor/Fastscan or Synopsys TetraMax.
4、Must have intimate knowledge and experience in ASIC design from RTL to timing verified layout.
5、Must have knowledge of Verilog RTL, simulators, Synopsys synthesis, Primetime static timing analysis, equivalence checker and debugging tools.
6、Must have participated in the successful development of complex ASICs, preferably in the consumer electronics space.
7、Must be a hands-on designer with proven track record required in utilizing industry standard ASIC design tools in the areas of verification, synthesis, DFT, and timing closure.
8、Must be a team player with excellent communications skills.
9、Must have skills for timely delivery of quality results working with cross-functional team members.
10、Knowledge of testing mixed signal designs.
11、Track record of delivering DFT solutions for SoC chips from concepts to tapeout.

公 司 简 介
世芯电子（上海）有限公司是由美国硅谷工程师创办的外商独资企业，主要提供Fabless ASIC芯片设计技术服务。我们拥有世界一流芯片设计的团队，多次为海外公司成功地提供了基于45纳米µm、低功耗工艺的大型高端芯片的设计服务。
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About Us
Alchip Technologies Limited was founded in 2002 by semiconductor veterans from Silicon Valley and Japan with a business focus on turnkey fabless ASIC production for System-on-Chip (SoC) designs. The founding team has more than fifteen years experience on average in successfully developing high-complexity SoC products and has 100% first silicon success track record.

As chip complexity increases and process technology advances, physical design becomes the bottleneck of chip creation. According to Collett International Research, more than 65% of IC/ASIC designs required re-spins in 2003, seriously impacting product schedule and putting companies under tremendous time-to-market pressure. With excellent design expertise and proven SoC design methodology, Alchip enables customers achieve one-pass silicon success and therefore meet customers faster-time-to-market.

In addition to enabling customers faster-time-to-market, Alchip also helps customers reduce cost through design and product engineering. Facing today’s competitive markets, most semiconductor companies are under great cost pressure. Alchip endows customers cost advantage over competitors in the increasingly competitive markets.

In summary, customers will be able to focus on chip functionality and system design by outsourcing physical design and chip production to Alchip. Alchip’s leading-edge solutions ensure customers faster time to market and improved cost efficiency. It is a win-win for both sides.

Alchip currently has offices in Silicon Valley, Shin-Yokohama, Hsin-Chu, Taipei,Shanghai, Wuxi, Hefei,Guangzhou,Jinan.