上海招聘

职位描述：
ob description
As a Senior IC Layout Engineer at Calterah Semiconductor, he/she will be responsible for layout and physical verification of key analog and RF blocks in advanced CMOS technology nodes. He/she will work with IC team to meet scheduled deadlines, performing layout, verification and final GDS preparation of the entire IC.

Responsibilities
? Full custom analog layout/verification and RC extraction.
? Perform block and top level layout. Conduct physical verification (DRC and LVS using Cadence tools).
? Team work with analog designers, optimize layout.
? Prepare LEF for digital PR and integrate PR blocks into SoC.
? Prepare GDS database for tapeout.

Skills required
? 3+ years experiences in CMOS analog/RF/mixed-signal block layout.
? Experience in mass production CMOS wireless chip layout.
? Familiar with layout skills and Cadence CAD tools.
? Familiar with advanced CMOS nodes 65nm/40nm/28nm.
? Able to work with digital team to achieve final SoC integration.
? Good teamwork/communication/positive is must.

Education
Bachelor required; 举报 分享

加特兰微电子科技是由美国硅谷海归博士创立的无晶圆集成电路设计企业。公司专注于研发高级驾驶辅助系统及无人驾驶系统中的核心传感器芯片，并立志成为行业内技术领先世界的中国企业，为大众市场提供高性价比的主动安全核心技术。加特兰微电子由国际知名风险投资机构投资。

Calterah Semiconductor is a fabless semiconductor startup founded by pioneers in the field of high frequency CMOS from the University of California, Berkeley and the Silicon Valley. The company focuses on developing high performance sensor technology for Advanced Driver Assistance Systems (ADAS) and various autonomous vehicles. It aims to be a leading semiconductor technology company worldwide, with a mission to provide affordable safe mobility for the mass market. The startup is backed by top tier semiconductor venture capital firms.