南通招聘

Your Responsibilities:
1. Carry out all MCU development activities in the field of digital back-end design on own initiative
2. Perform chip die size estimation in the product definition phase, and generate chip floorplan based on early stage netlist and perform improvement according to netlist updating
3. Generate chip layout with Cadence tools, by performing placement and routing
4. Generate clock tree with Cadence tools and perform timing improvement with feedback from timing analysis
5. Perform physical verification like DRC and LVS and perform chip releasing and PCM
6. Communicate within a design team and within the whole development organization
7. Guarantee the technical deliverables of his jobs in terms of quality and performance
8. To develop his/her leadership on his/her domain of skills and actions
Your Profile:
1. MSEE or BSEE, English understanding/speaking/writing
2. Minimum of 3 years experience for layout design
3. Familiar with and has the design experience Cadence layout design tools: Encounter, Virtusuo, PCM, etc
4. Specific knowledge of the relevant technical areas, e.g. multi-power domain place & routing, etc
5. Able to establish good relationships with a multi-disciplinary development team, international customers and subcontractors
6. Creative thinker with helicopter view, capable of finding an appropriate solution to complex problems

关于大唐恩智浦半导体有限公司
大唐恩智浦半导体有限公司，成立于2014年3月，是中国首家汽车半导体公司。公司由大唐电信科技股份有限公司与全球领先的半导体安全连接解决方案供应商荷兰恩智浦半导体有限公司共同出资成立。公司业务定位于新能源汽车，混合动力汽车电源管理和驱动，以及新能源相关的集成电路设计领域，专注于研发和销售采用高性能混合信号技术的高级专用汽车电子IC，致力于成为全球领先的汽车半导体公司。更多信息请访问公司官网：www.datangnxp.com