Senior ASIC Design Engineer
美满电子科技（Marvell）
- 公司规模：500-1000人
- 公司性质：外资(欧美)
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2015-03-09
- 工作地点：北京-海淀区
- 招聘人数：若干
- 职位月薪：面议
- 职位类别：集成电路IC设计/应用工程师
职位描述
Job title: Senior ASIC Design Engineer
Location: Beijing
Department: Storage IC R&D
Job Description
1. Provide low power design scripts for front-end and back-end flow. Carry out low power verification and generate necessary ECO scripts.
2. Run voltage drop (IR drop) analysis on full chip and sub-block levels. Deliver analysis reports and work with back-end designers to improve voltage drop.
3. Run early stage power estimation and power structure design, such as power grid and power ring. Evaluate floorplan and power structure, deliver voltage drop analysis reports.
4. Run SPICE-level voltage drop analysis on hard macros. Deliver analysis reports and work with custom designers to improve voltage drop.
Requirements
1. 2+ years industry working experience with EE/ME or background in related areas.
2. Knowledge of low power design techniques, such as power gating, DVFS, RTL level power optimization.
2. Experience in two or more of the following areas:
Low power design and verification in either front-end or backend with UPF/CPF.
Back-end design flow, such as floorplan, PNR, DRC, LVS and extraction.
Power analysis with tools like PTPX, Redhawk, XA-RA, Totem.
Digital custom design working with schematic and layout.
3. Experience in one or more of the following techniques will be a plus:
SPICE simulation
Verilog simulation
Scripting with Tcl/Python/Perl
4. Good English skills, especially writing.
Location: Beijing
Department: Storage IC R&D
Job Description
1. Provide low power design scripts for front-end and back-end flow. Carry out low power verification and generate necessary ECO scripts.
2. Run voltage drop (IR drop) analysis on full chip and sub-block levels. Deliver analysis reports and work with back-end designers to improve voltage drop.
3. Run early stage power estimation and power structure design, such as power grid and power ring. Evaluate floorplan and power structure, deliver voltage drop analysis reports.
4. Run SPICE-level voltage drop analysis on hard macros. Deliver analysis reports and work with custom designers to improve voltage drop.
Requirements
1. 2+ years industry working experience with EE/ME or background in related areas.
2. Knowledge of low power design techniques, such as power gating, DVFS, RTL level power optimization.
2. Experience in two or more of the following areas:
Low power design and verification in either front-end or backend with UPF/CPF.
Back-end design flow, such as floorplan, PNR, DRC, LVS and extraction.
Power analysis with tools like PTPX, Redhawk, XA-RA, Totem.
Digital custom design working with schematic and layout.
3. Experience in one or more of the following techniques will be a plus:
SPICE simulation
Verilog simulation
Scripting with Tcl/Python/Perl
4. Good English skills, especially writing.
公司介绍
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.
Website: **********************
Website: **********************
联系方式
- Email：jiangrr@marvell.com
- 公司地址：地址：span安德门大街57号（楚翘城）7幢3层