Physical Design Engineer
美满电子科技(Marvell)
- 公司规模:500-1000人
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2014-04-28
- 工作地点:南京
- 招聘人数:若干
- 职位类别:集成电路IC设计/应用工程师
职位描述
Job title: Physical Design Engineer
Department: COT-PD
Location: Nanjing
Responsibilities:
As member of Marvell central physical design team, you will play a challenging role in assisting multiple Marvell design groups in sign-off check includes power/signal integrity analysis (IR drop, EM, ESD), physical verification (DRC/LVS/ERC/Antenna), chip-level layout and tapeout, as well as maintaining power analysis and physical verification flow, custom layout and add-on tools.
Requirements:
o 2+ years of direct experience on IC design. BS/MS preferred.
o Knowledge in some of the following technical areas: custom layout, PCB layout, power consumption calculate, timing, chip package.
o Proven track records of working independently on running and debugging chip-level DRC/LVS/ERC/Antenna results.
o Understanding of power planning, be able to analyze the weakness of power grid and provide solution.
o Be Familiar with Laker, Cadence Virtuoso, or Mentor DesignRev. Strong knowledge to debug Mentor’s Calibre or Synopsys’ Hercules tools.
o Be familiar with Apache, Encounter Power System, or PrimeRail.
o Must be programming-minded, capable of writing Tcl or Perl.
o Self-motivated team worker, good verbal and written communication skills.
o Knowledge of Cadence or Synopsys Place and Route tools a big plus.
o Must able to work under tapeout pressure and tight schedule.
Department: COT-PD
Location: Nanjing
Responsibilities:
As member of Marvell central physical design team, you will play a challenging role in assisting multiple Marvell design groups in sign-off check includes power/signal integrity analysis (IR drop, EM, ESD), physical verification (DRC/LVS/ERC/Antenna), chip-level layout and tapeout, as well as maintaining power analysis and physical verification flow, custom layout and add-on tools.
Requirements:
o 2+ years of direct experience on IC design. BS/MS preferred.
o Knowledge in some of the following technical areas: custom layout, PCB layout, power consumption calculate, timing, chip package.
o Proven track records of working independently on running and debugging chip-level DRC/LVS/ERC/Antenna results.
o Understanding of power planning, be able to analyze the weakness of power grid and provide solution.
o Be Familiar with Laker, Cadence Virtuoso, or Mentor DesignRev. Strong knowledge to debug Mentor’s Calibre or Synopsys’ Hercules tools.
o Be familiar with Apache, Encounter Power System, or PrimeRail.
o Must be programming-minded, capable of writing Tcl or Perl.
o Self-motivated team worker, good verbal and written communication skills.
o Knowledge of Cadence or Synopsys Place and Route tools a big plus.
o Must able to work under tapeout pressure and tight schedule.
公司介绍
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.
Website: **********************
Website: **********************
联系方式
- Email:jiangrr@marvell.com
- 公司地址:地址:span安德门大街57号(楚翘城)7幢3层