南京招聘

Candidate will be part of the front end team for the next-generation Marvell application processor targeted for the PDA and cell phone markets. Responsibilities include logic design, synthesis, and timing convergence. Interaction with other teams in different geographies will be a key skill in this position.


Job requirements/Responsibilities include:
·5+ years work experience in front end ASIC implementation methodology
·Strong understanding of synthesis flow using Design Compiler - for a low power (UPF) and high speed- complex SoC
·Hands on experience with formal verification tools such as LEC and/or formality
·Must have solid understanding of Clock Tree Synthesis using ICC
·Strong STA skills. Must have thorough knowledge on closing timing at unit and top level
·Ability to build new EDA-methodology-flow using perl, tcl and shell programming would be an added advantage


pls send your cv to marvellphs@gmail.com

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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