南京招聘

-- Complete design implementation flows and related QA signoff for IP and SoC: Synthesis, CTS, STA, LEC/CLP,  etc.

-- Support design automation to improve IP and SoC quality and efficiency

-- EDA flows, environment, and related QA define, develop, maintain, and enhancement.

-- Can support or lead other engineers

Requirements :

-- Master of EE, CS, or related fields.

-- More than 5~6 years working experiences.

-- Proficiency in design flows : Synthesis, CTS, STA, LEC/CLP,  etc.

-- Digital circuit, logic, and HDL (Verilog) design is plus.

-- DFT/ATPG, or Power, speed and area (PPA) optimization is a plus.

-- Successful track records of taping out complex chips at various technology nodes.

-- Experience with advanced nodes at 16nm and below is a plus.

-- Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.

-- Self-motivated, able to work as a team leader, excellent verbal and written communication skills in English.

南京凯鼎电子科技有限公司是世界领先的EDA和IP设计服务提供商，隶属于美国Cadence旗下。凯鼎以南京为中心，大力发展以IP设计开发和系统设计实现为中心的整体芯片设计解决方案和方法学解决方案，力争成为世界领先IP和系统设计实现公司。
在凯鼎，你可以接触到世界上先进的IP技术、世界上领先的工艺开发环境以及贴近市场的应用，成为芯片设计技术上的引领者。 凯鼎可以提供有竞争力的薪资和激励计划、专业的导师指导和完善的人才发展计划。