南京招聘

JD :

1.Responsible for design flow development including Synthesis, STA, DFT, APR, SI, IR, CTS, timing closure methodology development

2. flow automation, and project issue support/execution.

3. In-ouse EDA tool development

Require :

1. Experience in APR or DFT flow

2 .Familiar with Cadence EDI / Innovus or Synopsys ICC/ICC II or Design Compiler or PrimeTime or TetraMAX, DFTMAX or Mentor BIST or Calibre

3. Experience in chip implementation execution is plus

4. Good communication skill with Chinese and English

5. Knowledge with script and programming skills

6. C/C++ is plus

7. 40/28/16nm IC design experiences

8. 0-2+ years experience for engineer job

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