南京招聘

As a member of SoC PD team you will be in building state-of-the-art communication chips. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place&route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, ECO flow, with special focus on power & die size optimization.

Duties and Responsibilities:

• Responsible for RTL2GDS implementation of hierarchy designs, for both top and block level
• Participate in defining Physical and Timing Sign-Off conditions
• Work closely with RTL design team to understand the design architecture and drive design physical planning aspects
• As member of physical design team, drive methodologies and best known methods to streamline and automate physical design work
• Resolve design and flow issues related to physical design, identify potential solutions and drive execution
• Participate in technical and schedule discussions

· Participate in below block and top PD tasks

？ floorplanning

？ Placement and optimization

？ Clock tree synthesis and optimization

？ Routing and optimization

？ ECO

？ Parasitic extraction

？ Static timing analysis and timing closure

？ Full chip power analysis and convergence

？ Physical verification and chip tape out sign off

Qualified candidate should be with 5+ years of related work experience with a mix of technologies including:

• All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
• Hierarchical design implementation approach, Timing closure, physical convergence.
• Power Integrity Analysis
• Familiarity with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies

You should also have hands on experience with the following Tool sets

• Floor planning and P&R tools: Cadence Innovus & Synopsys ICC/ICC2
• Synthesis Tools: Synopsys DC/DCG
• Formal Verification : Synopsys Formality
• Static Timing verification: Primetime
• Power Integrity : Apache Redhawk
• Physical Design Verification: Synopsys ICV, Mentor Calibre
• Scripting: TCL, Perl is required; Python is a plus

Bachelor's or a Master s Degree in Electrical or Computer Engineering required

诺领科技是一家无晶圆厂IC设计公司，在加利福尼亚、深圳、北京、南京和香港设有分公司和办公室。我们拥有射频模拟、基带通信系统、GNSS、SoC系统和软件方面的顶尖人才，是探索满足IoT需求的全集成、低功耗无线SoC解决方案的先行者。诺领科技致力于提供***SoC解决方案，为下一代IoT通讯加足马力，同时帮助我们的客户赢得显著的成本和性能优势。公司目前推出的产品包括物联网系统级芯片NB-IoT和Cat-M SoCs，服务于广泛的市场，其中包括智慧城市、可穿戴设备、资产追踪等等。

公司地址：北京市海淀区中关村软件园5号汉王大厦