南京招聘

Maintain and help improve our UVM based verification environment.

Build verification package for modules and new functions, write testplan and add testcases to keep improving the verification coverage.

Research on some advanced verification technology such as assertion based formal verification.

Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 5+ years working experiences in ASIC design or verification. 

Familiar with Verilog and RTL design 

Familiar with System-Verilog and UVM verification methodology 

Familiar with script languages(perl,tcl,sh etc.) is a plus 

Familiar with digital signal processing knowledge is a plus 

Good problem solving and communication skills 

Good written and spoken English. Be able to work together with global team. 

We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.

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