Senior Asic Designer
无锡网芯科技有限公司
- 公司规模：50-150人
- 公司性质：民营公司
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2013-07-13
- 工作地点：无锡
- 招聘人数：2
- 工作经验：三年以上
- 学历要求：硕士
- 职位类别：电子技术研发工程师
职位描述
Responsibilities:
Lead design team to meet the objectives on design quality, time-to-market, and so on
Design complex Ethernet Switch ASIC products for Location and Communication applications including specification trade-offs and optimization, micro-architecture, pipeline partition, RTL coding, Synthesis, timing optimization, STA, chip testing and characterizationComplete block level design (spec to RTL to post layout timing verified gates)
Design of blocks such as MAC, SPI, DMA, State machines, high speed interfaces, etc
Develop clear design documentation
Develop both verification test suites and validation specifications
Assist in verification and validation testing
Required Skills:
MSEE degree preferably in Electronics and Communication field
Extensive working knowledge of networking protocols
3+ years of design/development experience in building network switch and router products
5+ years of experience in Verilog/Synthesis-based ASIC Design for mass production IC chips.
Strong domain knowledge in L2 and L3 Ethernet switching and routing covering 802.1Q VLANs, 802.1s MSTP, 802.3ad standards
Knowledge of integrating L2/L3 protocol stacks on Ethernet switching ASICs required
Development experience of management interfaces like SNMP, CLI, Web desirable
Solid experience in low level programming using C in Vxworks and Linux embedded platforms
Good understanding of architecture of Ethernet switching software preferable
Must have good hands-on experience with RTL coding, simulation and synthesis
Must have been closely involved with P & R, timing closure, DFT, and ATE test vector generation
Lead design team to meet the objectives on design quality, time-to-market, and so on
Design complex Ethernet Switch ASIC products for Location and Communication applications including specification trade-offs and optimization, micro-architecture, pipeline partition, RTL coding, Synthesis, timing optimization, STA, chip testing and characterizationComplete block level design (spec to RTL to post layout timing verified gates)
Design of blocks such as MAC, SPI, DMA, State machines, high speed interfaces, etc
Develop clear design documentation
Develop both verification test suites and validation specifications
Assist in verification and validation testing
Required Skills:
MSEE degree preferably in Electronics and Communication field
Extensive working knowledge of networking protocols
3+ years of design/development experience in building network switch and router products
5+ years of experience in Verilog/Synthesis-based ASIC Design for mass production IC chips.
Strong domain knowledge in L2 and L3 Ethernet switching and routing covering 802.1Q VLANs, 802.1s MSTP, 802.3ad standards
Knowledge of integrating L2/L3 protocol stacks on Ethernet switching ASICs required
Development experience of management interfaces like SNMP, CLI, Web desirable
Solid experience in low level programming using C in Vxworks and Linux embedded platforms
Good understanding of architecture of Ethernet switching software preferable
Must have good hands-on experience with RTL coding, simulation and synthesis
Must have been closely involved with P & R, timing closure, DFT, and ATE test vector generation
公司介绍
无锡网芯科技有限公司成立于2009年1月，是一家主要从事集成电路及计算机软件的设计、测试和销售的公司。公司是由多名在美国从事芯片研发的资深芯片工程师及国内众多资深工程师共同组成的最具竞争力的核心群体。
我公司主要致力于网络芯片研发，技术力量雄厚，使用先进的工艺创造高速，安全的新一代网络。我们是一支具备丰富知识与丰厚经验的高素质团队。在全体研发工作者中，本科学历占51.2%，硕士学历占48.8%。
公司发展至今，已获得ISO27001体系认证、软件企业认定证书、集成电路设计企业认定证书、多项发明专利等一系列成就。
严格、规范的质量控制体系是我们的保障；
雄厚的科研技术力量是我们的核心；
良好的中西结合的企业文化是我们的特色；
健全的人才激励机制是我们发展的不竭动力；
国际一流IC企业是我们永恒的目标与追求。
我公司主要致力于网络芯片研发，技术力量雄厚，使用先进的工艺创造高速，安全的新一代网络。我们是一支具备丰富知识与丰厚经验的高素质团队。在全体研发工作者中，本科学历占51.2%，硕士学历占48.8%。
公司发展至今，已获得ISO27001体系认证、软件企业认定证书、集成电路设计企业认定证书、多项发明专利等一系列成就。
严格、规范的质量控制体系是我们的保障；
雄厚的科研技术力量是我们的核心；
良好的中西结合的企业文化是我们的特色；
健全的人才激励机制是我们发展的不竭动力；
国际一流IC企业是我们永恒的目标与追求。