Senior IC Design Verification Engineer
上海世谛集成电路设计有限公司
- 公司规模：50-150人
- 公司性质：外资（欧美）
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2016-11-04
- 工作地点：上海-浦东新区
- 招聘人数：1人
- 学历要求：本科
- 职位月薪：15000-19999/月
- 职位类别：IC验证工程师
职位描述
职位描述：
Requirements:
The candidate is preferred to be MSEE with minimum of 2 years, or BSEE with minimum of 4 years experience in digital ASIC/SOC design verification. The candidate should have good understanding on ASIC/SOC design flow and should have:
1. Good knowledge of design verification methodology, such as VMM or OVM.
2. Many experiences with simulation model creation and the testbench build
3. Strong RTL coding with Verilog and familiar with front-end design flow
4. Strong C/C++ software development experiences
5. Be familiar with scripting language, such as Perl, C shell, Makefile.
It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Responsibility:
The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
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Requirements:
The candidate is preferred to be MSEE with minimum of 2 years, or BSEE with minimum of 4 years experience in digital ASIC/SOC design verification. The candidate should have good understanding on ASIC/SOC design flow and should have:
1. Good knowledge of design verification methodology, such as VMM or OVM.
2. Many experiences with simulation model creation and the testbench build
3. Strong RTL coding with Verilog and familiar with front-end design flow
4. Strong C/C++ software development experiences
5. Be familiar with scripting language, such as Perl, C shell, Makefile.
It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Responsibility:
The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
职能类别： IC验证工程师
公司介绍
创建于2003年的Synapse是世界上较大的芯片设计、系统设计和软件开发的设计咨询公司。 截止到2011年底,我们在全球拥有600名经验丰富的员工。公司的总部位于美国加州硅谷的圣何塞, 中国上海(中国总部), 北京, 印度班加罗尔等地设有设计和销售中心。
Synapse China(上海世谛集成电路设计有限公司) 是Synapse美国总公司全资拥有的一家子公司，于2010年3月在上海成立。到目前为止，已经成为在中国市场发展最快的一家设计服务公司。中国子公司自成立起，已经拥有了多家国际客户
Synapse China(上海世谛集成电路设计有限公司) 是Synapse美国总公司全资拥有的一家子公司，于2010年3月在上海成立。到目前为止，已经成为在中国市场发展最快的一家设计服务公司。中国子公司自成立起，已经拥有了多家国际客户
联系方式
- 公司地址：地址：span张江高科技园