杭州招聘

【Responsibilities】

1. Expertise in handling Netlist to GDS2 flow.

2. Implement the place and route of design blocks including floorplaning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, formal verification, power intent checks etc.

3. Responsible for block/chip level physical design closure interms of timing, power, DRC/LVS etc.

4. Flow automation using one of script programming languages, perl, python, tcl or makefile.

【Requirements】

1. 3/5+ years experience in complex ASIC design projects

2. Deep knowledge of entire physical design process from floorplan till GDS generation。

3. Good exposure to physical verification process.

4. Experience in leading PnR tools, Synopsys ICC2 or Cadence Inovus.

5. Hand on experience in latest sub-micore technologies below 40nm.

6. Experience in ECO implementation.

7. Proficient in one of script programming languages, perl, python or TCL.

8. Experience in low power designs and handling congestion or timing critical tiles will be preferred.

Education/Certifications

Preferred Degree: MS Preferred Major: Microelectronics or related discipline

加特兰微电子科技是由美国硅谷海归博士创立的无晶圆集成电路设计企业。公司专注于研发高级驾驶辅助系统及无人驾驶系统中的核心传感器芯片，并立志成为行业内技术领先世界的中国企业，为大众市场提供高性价比的主动安全核心技术。加特兰微电子由国际知名风险投资机构投资。

Calterah Semiconductor is a fabless semiconductor startup founded by pioneers in the field of high frequency CMOS from the University of California, Berkeley and the Silicon Valley. The company focuses on developing high performance sensor technology for Advanced Driver Assistance Systems (ADAS) and various autonomous vehicles. It aims to be a leading semiconductor technology company worldwide, with a mission to provide affordable safe mobility for the mass market. The startup is backed by top tier semiconductor venture capital firms.