杭州招聘

【responsibilities】

1. Block and full-chip level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation).

2. Develop and maintain methodology and flows related to timing verification and closure.

3. Generate block and full chip level timing constraints.

4. Resolve complex timing issues for major building blocks of complex SoCs.

【Requirements】

1. 3/5+ years' experience in ASIC timing constraint generation and timing closure.

2. Thoroug knowledge of the ASIC desig ntiming closure flow and methodology.

3. Experience in STA tools and flows.

4. Knowledge of timing corners/modes, process variations and signal integrity related issues.

5. Hand on experience in timing/SDC constraints generation and management.

6. Proficient in scripting languages (TCL and Perl)

7. Strong ability in constraint analysis and debug, using industry standard tools such as Synopsy GCA

8. Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and bist testing

加特兰微电子科技是由美国硅谷海归博士创立的无晶圆集成电路设计企业。公司专注于研发高级驾驶辅助系统及无人驾驶系统中的核心传感器芯片，并立志成为行业内技术领先世界的中国企业，为大众市场提供高性价比的主动安全核心技术。加特兰微电子由国际知名风险投资机构投资。

Calterah Semiconductor is a fabless semiconductor startup founded by pioneers in the field of high frequency CMOS from the University of California, Berkeley and the Silicon Valley. The company focuses on developing high performance sensor technology for Advanced Driver Assistance Systems (ADAS) and various autonomous vehicles. It aims to be a leading semiconductor technology company worldwide, with a mission to provide affordable safe mobility for the mass market. The startup is backed by top tier semiconductor venture capital firms.