版图设计工程师
上海季丰电子有限公司
- 公司规模:少于50人
- 公司性质:民营公司
- 公司行业:电子技术/半导体/集成电路 计算机硬件
职位信息
- 发布日期:2012-11-12
- 工作地点:杭州-西湖区
- 招聘人数:若干
- 工作经验:五年以上
- 学历要求:本科
- 语言要求:英语精通
- 职位类别:版图设计工程师
职位描述
我们的客户是一家世界顶尖半导体设计公司,位于杭州西湖区的设计团队中需要招收多名模拟电路Layout工程师,具体要求如下:
Compete in a wide range of markets including:
[1]DC/DC Converters
[2]High Resolution Data Conversion
[3]Interface Products
[4]Portable Power Management
[5]Hot Swap Controllers
[6]High Performance Amplifiers and References
[7]Automotive Electronics
Responsibilities include (but are not limited to):
1.Layout schedule estimation.
2.IC layout floor planning.
3.Layout of analog and digital circuits.
4.Cell level verification and parasitic extraction.
5.Chip/Top level routing and interconnect.
6.LVS and DRC checks using Cadence Dracula and Assura.
7.Tape out/Stream out/PG.
Qualifications:
1.Associates or bachelor’s degree in Electrical Engineering.
2.Five years of relevant IC layout experience.
3.Strong background in analog layout.
4.Familiarity with Cadence tools (Virtuoso, Layout XL, Assura, Dracula).
5.Layout experience with bipolar, CMOS, and BiCMOS technologies.
6.Working knowledge of Linux operating systems.
7.Experience with full chip layout including PG to the mask shop.
8.Knowledge of semiconductor device and fabrication principles is a plus. 9.Ability to work independently.
10.Great attention to detail, communication skills, well organized
女士优先!
Compete in a wide range of markets including:
[1]DC/DC Converters
[2]High Resolution Data Conversion
[3]Interface Products
[4]Portable Power Management
[5]Hot Swap Controllers
[6]High Performance Amplifiers and References
[7]Automotive Electronics
Responsibilities include (but are not limited to):
1.Layout schedule estimation.
2.IC layout floor planning.
3.Layout of analog and digital circuits.
4.Cell level verification and parasitic extraction.
5.Chip/Top level routing and interconnect.
6.LVS and DRC checks using Cadence Dracula and Assura.
7.Tape out/Stream out/PG.
Qualifications:
1.Associates or bachelor’s degree in Electrical Engineering.
2.Five years of relevant IC layout experience.
3.Strong background in analog layout.
4.Familiarity with Cadence tools (Virtuoso, Layout XL, Assura, Dracula).
5.Layout experience with bipolar, CMOS, and BiCMOS technologies.
6.Working knowledge of Linux operating systems.
7.Experience with full chip layout including PG to the mask shop.
8.Knowledge of semiconductor device and fabrication principles is a plus. 9.Ability to work independently.
10.Great attention to detail, communication skills, well organized
女士优先!
公司介绍
上海季丰电子有限公司(Giga Force)成立于2008年,是一家为集成电路产业提供整合服务和全方位解决方案的高科技公司,客户包括世界级及当地知名的设计公司,晶圆制造厂,封装测试厂和研究院所等,。
公司主要业务有用于集成电路成品测试的承载板(Load Board)、晶圆(wafer)测试的探针卡(probe card)、集成电路老化测试的老化板等高端多层线路板(10层到50层)的设计整合等,以及集成电路产品前端的设计开发(Netlist/schematic design service),后道集成电路产品的验证分析、老化测试等可靠性整合服务等,并持续引入新的产品线。
公司经过多年的发展,建立了一支经验丰富的技术团队,在数字信号,模拟信号,混合信号,RF信号以及高速信号,以及在多层板,多site,盲埋孔,Micro BGA,等长线、单端和差分线的阻抗控制方面积累了丰富经验,得到客户广泛认可,业绩连续多年持续快速增长。
公司主要业务有用于集成电路成品测试的承载板(Load Board)、晶圆(wafer)测试的探针卡(probe card)、集成电路老化测试的老化板等高端多层线路板(10层到50层)的设计整合等,以及集成电路产品前端的设计开发(Netlist/schematic design service),后道集成电路产品的验证分析、老化测试等可靠性整合服务等,并持续引入新的产品线。
公司经过多年的发展,建立了一支经验丰富的技术团队,在数字信号,模拟信号,混合信号,RF信号以及高速信号,以及在多层板,多site,盲埋孔,Micro BGA,等长线、单端和差分线的阻抗控制方面积累了丰富经验,得到客户广泛认可,业绩连续多年持续快速增长。
联系方式
- 公司地址:上班地址:上海市浦东新区祖冲之路1505弄55号1楼