CPLD Frimware design Engineer
捷普集团-捷普科技(上海)有限公司 Jabil Circuit (Shanghai) Ltd.
- 公司规模:10000人以上
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2019-06-19
- 工作地点:上海-徐汇区
- 招聘人数:1人
- 工作经验:5-7年经验
- 学历要求:本科
- 职位月薪:1.5-3万/月
- 职位类别:电子工程师/技术员
职位描述
SUMMARY
Take the major responsibility for FPGA/CPLD code development, maintain & version control for Server & Storage, Networking, Telecom product projects. Provide necessary inputs to validation engineers for product design quality assurance. Drive innovation and continuous improvement within Jabil Circuit by harnessing new design technologies and methodologies. Provide exceptional support to external and internal customers, team members, and other persons through technical project coordination.
ESSENTIAL DUTIES AND RESPONSIBILITIES include, but are not limited to the following:
1. Design and implement software and systems of CPLD/FPGA devices from requirements to production and commercial deployment;
2. Development of Verilog/VHDL for FPGAs;
3. Integration with other system hardware and software components;
4. Analyze and enhance efficiency, stability and scalability of system resources;
5. Integrate and validate x86 platform server & JBOD, telecom, swtich product designs;
6. Support system design and optimise I/O performance;
7. System power sequence and reset logic control development.
8. Low/high speed IO interfaces development. (I2C/SPI/UART/ADC/LPC,etc).
9.Be esponsible for CPLD issue troubleshooting from design to maintain. Leverage ODM/ vendor resource to give a right solution for the bug.
10. Provide post production support;
Person Background:
1. 3+ years experience writing in Verilog/FPGA in a product development environment: ISE, Quartus.
2. Demonstrated history of success in developing large, high quality FPGA designs.
3. Experience using any FPGAs of the following venders: Xilinx, Altera, Actel, Lattice.
4. Strong skills in RTL coding, simulation, synthesis, timing analysis and debugging using Verilog/VHDL.
5. Experience using emulators, debuggers, scopes, logic analyzers, and protocol analyzers to locate and resolve firmware-hardware interaction issues.
6. Understanding of high speed board design techniques along with knowledge of signal integrity fundamentals.
7. Good knowledge of ACPI, SMI, SCI, APM, SMART, Hyper Transport, Intel LFBP, Intel Speed-step, MPS tables, Net-boot, PCI Express config & routing, PXE, S1-S4 sleep, Serial Flash, SMBUS & SMBIOS, USB2.0, User ROM, WFM etc.
8. Fluently English communication skill with internal team and external vendor.
9. Demonstrated ability to work in a small, fast paced team to meet challenging project deadlines.
Person Attributes:
The successful candidate will be a self-motivated individual capable of working with a minimum of supervision in a dynamic team environment. Good interpersonal skills: be able to communicate in English and with members of other teams, departments and clients; as a high degree of liaison is needed.
职能类别: 电子工程师/技术员
公司介绍
为确保我们能继续创造经济效益和增长,我们已在多个市场开展运营,包括售后服务、计算与存储、国防与航空、医疗与仪表制造、工业和清洁技术、材料技术、移动通信、网络和电信。此策略已取得成功 — 在十多年内,我们通过坚定不移地致力于适当结合服务、行业、位置、系统和人员,已取得了两位数的增长。Jabil 已使用 “JBL” 代码在纽约证券交易所上市,我们欢迎未来的员工查阅公司的财务概况。
我们为有资历的个人提供平等的雇用机会,无论其种族、宗教、肤色、年龄、国籍、性别、残疾和性取向如何。我们将员工技能、能力、经验和背景的多样化视为一项优势,并在 Jabil 的所有领域中鼓励发挥该优势。
我们主张聘用适当的人员、将他们安排在能贡献一己之力的职位,并为他们提供决策所需的工具和职权。如果您对所做的一切都秉持质量***的心态,且对取得成效充满热情,那么 Jabil 是您的不二之选。
欲更详细了解公司情况,请登录本公司网站。如果您有意应聘所述岗位,请将中英文简历及相关证书复印件选择所述方式寄至公司,并请注明相关应聘职位。来信请寄至本公司。未经录用者,简历恕不退回。谢谢!
公司网站 : ********************
联系方式
- Email:duan@jabil.com
- 公司地址:上海市田林路600号 (邮编:200233)