合肥招聘

Responsibilities:

1. Take charge DFT flow of SOC product.

include stuck-at/at-speed scan, memory BIST, ATPG and so on.

2. Take charge product MP test and yield control.

Requirements:

1. Familiar with mainstream DFT tool & flow, such as Synopsys/Mentor.

2. Familiar with Verilog HDL,VCS, NC verilog etc simulation tools;

familiar with SOC synthesis flow, experience on STA flow.

3. Familiar with analog IP test methodology, such as ADC/DAC, PLL, USB PHY...

4. Experience in MP test, familiar with various ATE tester is a plus.

5. Good team spirit & communication skill.

6. M.S. Degree or above in Electrical Engineering or Computer Science. Major in Microelectronics is a plus.