合肥招聘

We are seeking a Principal ASIC Lead Design Engineer to join our ASIC/FPGA team. The candidate will hold the technical lead/architect role in a small ASIC design team and will have a great opportunity to utilize his/her technical skills to help set direction, influence strategy and provide leadership on new and challenging ASIC programs. In this role, the selected candidate will invlov all areas of digital design including chip architecture, RTL, implementation, synthesis, validation, ASIC bring-up, and characterization. In this position you will work with Marketing, Hardware, and Software organizations on partitioning and refining the architecture. The Principal Engineer is also responsible for coaching team of ASIC engineers throughout the implementation phase, device bring up, and release to production.
? Apply advanced technical principles, theories, concepts and provide solutions which are highly innovative and inventive, are on scope, on time, on cost and on quality
? Work collaboratively with the Marketing team on requirements development to ensure alignment with customer needs, available technology, time to market, resources and cost
? Work with program manager and the team on project planning: work scope development, staff assignment, schedule development, risk assessment etc
? Work closely with verification leads to develop chips verified to maintained specifications and work with a backend lead to realize physical design
? Lead architecture and design during all phases of the product cycle from concept to volume production including requirements definition, architecture development, design partitioning, interface definition, clock & reset strategy, high speed RTL design/implementation, synthesis, power optimization, pre and post-silicon validation, and chip bring-up and characterization
? Proven technical leadership experience with a minimum of 15 years of industry experience and five successful chip designs from concept to production
? Experience in requirements development, high level architecture, die-sizing and package evaluation, RTL coding, synthesis, constraint development, design for test, floor planning, timing closure, power analysis and optimization, signal integrity checks and final design signoff and strong familiarity with place and route
? Strong familiarity with modern constrained, random functional coverage based verification
? Domain experience in packet processing, filtering and serial links desired
? Experience with 40nm and 28nm design implementation highly desirable
? AdvancedVerilog RTL coding and Perl programming skills
? Synthesis using Cadence and/or Synopsys tool suite
? Timing analysis using Cadence and/or Synopsys Primetime tool, and timing closure
? DFT concepts including JTAG, Scan, ATPG, BIST
? Knowledge of data path optimization a plus
? FPGA and/or PCB experience also highly desirable
? Must be self-driven with good project management and problem solving
skills to deliver high quality output in a timely manner
? Must be a team player with good verbal and written communication skills
Qualification
? M.S in Electrical Enginering, Ph.D preferred
? 10+ experience in the architecture, design, and verification of ASICs for volume production
? Expertise with ASIC design methodology including Verilog Coding, Chip Constraints, Verification, Synthesis and timing closure
? Expertise with advance IC design technologies (Design, Process, Test, Package)
? Knowledge of low-level communications protocols in USB, PCIe, SATA, Ethernet, HDMI, DP desired
? Chip bring up experience
? Experience with Digital Signal Processing, clock data recovery, channel equalization, ADC, DAC a plus
? Mixed Signal experience preferred


在ASIC设计团队中承担技术领导和架构师的角色，在面对新的或具有挑战性的专用集成电路设计项目时，能发挥领导能力和专业技术水平，帮助团队设定设计方向、制定项目实施战略等。
? 能承担包括芯片结构、RTL、安装启用、合成、验证、ASIC启用和特色化设定等所有领域数字设计。
? 在优化架构和分区方面上能很好的处理和市场、软件、硬件团队的合作关系。
? 在实施和设备启动阶段的整个过程中，培训ASIC工程师并将能指导团队成员将培训结果应用到产品中。
? 利用先进的技术原则、理论和概念从范围、时间、成本和质量等角度提出创新性的解决方案。
? 和市场部携手合作，确保需求开发与客户需求、投放市场时间、现有技术能力及资源和成本等相匹配。
? 和项目经理及团队一起制定项目计划，工作内容涉及，工作领域开拓、任务分配、日程安排及风险评估等。
? 密切配合验证领导，使需验证的芯片符合既有的规范，同时能配合后端领导完成实体设计。
? 负责从概念到批量生产整个产品周期内各阶段的架构和设计工作， 包括：需求定义、架构开发、模块化设计、接口定义、记录及重新设定策略、高速RTL设计和实施、合成、功率优化、前后硅验证、芯片启用和个性化。

任职资格：
? 至少15年工业企业验证技术领导岗位工作经验和5个从概念到产品的成功芯片设计案例。
? 在需求开发、高层次架构、模具定性和包装评估、RTL代码编写、合成、压缩开发、可测性设计、平台规划、定时闭合、功率分析和优化、信号整合检查、设计结果核批方面有丰富的工作经验，并十分熟悉布局布线工作。
? 熟悉基于验证的调制解调器限制和随机的功能覆盖工作。
? 具有丰富的分组处理、过滤和串行电路领域工作经者优先考虑。
? 具有40nm和28nm设计执行经验者优先考虑。
? 具有高级代码RTL编写和编程技能。
? 能使用Cadence and/or Synopsys工具组件进行合成 操作
? 能使用Cadence and/or Synopsys Primetime工具进行时序分析和时间闭合
? 了解DFT概念，包括：JTAG, Scan, ATPG, BIST。
? 有数据路径优化知识者更佳。
? 有FPGA and/or PCB项目经验者更佳。
? 工作积极主动，具有优秀的项目管理能力和解决问题的能力，能及时提交高质量的工作成果。
? 优秀的口头和书面表达能力，适应团队工作。

资质
? 电子工程学研究生以上学历。
? 10年以上大规模生产的ASICs架构、设计和验证工作经验。
? 娴熟的ASIC设计方法包括：代码编写、芯片压缩、验证、合成和时序闭合。
? 熟练的先行集成电路设计技术（设计、加工、测试和包装）。
? 具有USB, PCIe, SATA, Ethernet, HDMI, DP低级通讯协议知识者优先考虑。
? 具有芯片启动工作经验。
? 具有数据信号处理、记录数据恢复、信道均衡和ADC、DAC操作经验。
? 具有混合信号处理经验者更佳。

    u安徽虹庄微电子有限公司于2012年3月在安徽合肥的高新技术开发区成立，公司定位于具有自主知识产权的集成电路、软件、整体解决方案和电子产品及服务提供商，目前公司致力于开发先进的高速接口技术以及应用系统。公司的首代产品为超高速 USB3.0设备控制器IP，在USB3.0设备控制器IP的研发完成后，公司将围绕自己已掌握的USB3.0 IP核心技术，以存储、移动多媒体、个人信息终端为主攻方向，开发新一代的移动存储产品，打造全新的移动终端新概念和物理平台，瞄准个人移动计算平台的新架构，以芯片和软件为支撑，成为下一代移动存储产品和个人信息终端的领跑者。

致精英们：应聘者需完全符合我公司招聘要求！条件更优越者，公司考虑股权激励办法！请了解！