SOC Verification Engineer
灿芯半导体(上海)有限公司
- 公司规模:150-500人
- 公司性质:外资(非欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2020-08-20
- 工作地点:合肥-高新区
- 招聘人数:若干人
- 工作经验:5-7年经验
- 学历要求:本科
- 职位月薪:2.5-4万/月
- 职位类别:IC验证工程师 FPGA原型验证工程师
职位描述
understanding the digital designs(Chip & IP);
Developing verification and regression plans;
Designing and developing verification environment;
Running RTL and gate level simulation/regression;
Coworking with Design&FPGA team;
Code/functional coverage development, analysis and closure;
Job Qualification:
Minmum of 5 years verification experience;
Knowledge in asic design process and verification tools/env (UVM);
Familiar with design and verification languages(verilog, System Verilog, SVA etc.);
Familiar with Simulation & Debug Tools(VCS, Verdi, etc.);
Familiar with ASIC Design Flow;
Scripting skills (perl, tcl, makefile, Python etc.) is a plus;
Experience in SOC chip level verification, including test plan and testbench development, test case development;
Additional qualifications include: Good Ic verification skills and basic knowledge of logic or circuit desing, good communication and problem solving skills;
职能类别:IC验证工程师FPGA原型验证工程师
公司介绍
我们的事业前途极富竞争力,并提供良好的工作环境、优厚的福利待遇和广阔的个人职业发展空间。因业务发展需要,我们诚邀微电子、半导体及电子类相关专业人才加盟。
敬请递交详尽个人简历,对符合条件的候选人,公司会尽快安排面试,择优录用。
Brite Semiconductor was founded in 2008 in Shanghai's Zhangjiang Hi-tech district, and is a fast growing SoC and ASIC Design Company aimed at assembling the most optimum IP, foundry, test and packaging technologies to create custom silicon solutions for its customers. Brite is committed to delivering electronics solutions with leading edge North American technology, competitive pricing, uncompromising quality and a customer-centric approach to meet all of a customer's ASIC needs.
Brite utilizes the Open Model to provide flexible, direct, and cost effective designs that reduce a chip's time to market. Focused on the customer's needs, Brite's comprehensive customer support supplements turnkey spec-parts solutions, third party manufacturing service, product OEM solutions, and all other design service solutions. Brite's unique MAX technology lowers costs and maximizes yields for advanced 40/45 nm designs. With a proven track record of first time silicon success and the experience of over 200 tapeouts, Brite ensures minimum risk in both frontend and backend physical design, as well as test engineering, packaging and assembly, wafer fabrication, and production support to be our customers' ideal all inclusive ASIC partner
联系方式
- 公司地址:地址:span张江高科张东路1158号2号楼7楼