合肥招聘

职位描述：
Description:
Physical Design for ASIC products
Perform floor-planning, physical synthesis, clock tree and clock gating design, power gating, routing, layout, integration and physical verification
Solve deep sub-micron design problems such as leakage, power, signal integrity, DFM, DFT etc.
Interact with Logic designers, AMS designers and internal/external IP teams
Work proactively with EDA engineers and tool suppliers to debug tool functionality and bugs

Qualification:
２＋years of experience and minimum of BS in in EE or equivalent; MS a plus
Complete knowledge of full design IC implementation and signoff process including design constraint generation, RTL Synthesis, floor-planning, cell placement, cock tree creation, SDC, routing, optimization, timing/drc closure and design signoff
Experienced with using Cadence Encounter, Synopsys ICC, ETS, Prime Time, PVS, QRC, Calibre, XRC, Hercules, StarRC etc.
Proficient in STA, power analysis, DRC/LVS/PEX/DFM, noise, static and dynamic IR drop analysis
Good UNIX background and Perl/Shell/SKILL scripting skills
Good written and verbal communication capability and proficient in both English and Mandarin
Strong time management and multi-tasking skills that enable on-time delivery
Experienced in working with analog circuits and transistor level layout designers
Familiar with design and layout of logic or analog circuits using Cadence Virtuoso or other tools
Familiar with digital design tools such as RTL Compiler, DFT, MBIST etc. 举报 分享

合肥灿芯科技有限公司是由灿芯半导体和合肥政府在2016年合资成立，定位于130nm/90nm以下的高端设计服务与Turn-Key服务，为客户提供从源代码或网表到芯片成品的一条龙服务。
灿芯半导体是中国最大的SoC和ASIC设计服务公司之一，由中芯国际集成电路制造有限公司投资。