东莞招聘

Responsibility （工作职责）:

• In charge of chip physical implementation from netlist to GDS2, including floor planning, power grid design, place and route, clock tree synthesis, SI/timing closure, , Top layout integration, DFM/DFY, physical verification (DRC/LVS/Antenna) to tape-out

  负责芯片的后端物理实现，从NETLIST到GDS2，包括floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, Top layout integration, DFM/DFY, physical verification (DRC/LVS/Antenna) 一直到流片

• Work closely with design team in Timing constraint , Interface, timing sign-off, IR drop Analysis to ensure successful tape-out

  和设计团队紧密合作，对时序约束，接口, 时序验收和IR drop把关以确保成功流片

Qualifications （职位要求）:

• BS/MS in EE with at least 3+ years of hands-on experience in back-end/physical design and timing closure, and familiar with digital design flow.

  3年以上数字后端和时序收敛的工作经验，熟悉数字设计流程，电子工程本科以上学历。

• Successful track record of SOC chips tape-out, mixed-signal layout experience is preferred

  具有大规模芯片流片经验，有mixed signal layout经验者优先

• Must be a power user of either Synopsys suite (IC Compiler), Cadence suite (EDI or Innovus).

  必须是使用Synopsys或者Cadence 自动布局布线工具的老兵

• Solid knowledge of static timing analysis, scripting experience in Perl/TCL

  理解时序/分析和优化，能使用tcl/perl编写脚本

• Good Teamwork collaboration & excellent communication capability

  良好的团队合作能力和表达沟通能力

微信分享