东莞招聘

  

• Chip Design Engineers are working on cutting-edge SoC (System on a Chip), ASIC, High Performance Processor, Chipset, Digital/Analog and Mix-signal Circuit IP design for our clients.

• Employ the industry leading tools, state of the art methodology, and innovative semiconductor technologies ranging from 45nm to 14nm and beyond

• Responsible for RTL to GDS flow including CPF definition, logic/physical synthesis, die size estimation, floor-planning, power planning, CTS, place and route, STA, signal integrity, timing closure, formal verification, DFM, DRC/LVS etc

• Back-end implementation and optimization for complex SOC designs

• Development of package and electrical design,

• Electronic Design Automation (EDA) & methodology development and deployment

• Play a critical role in high performance design timing closure

• Develop scripts for performing both functional and timing ECO’s.

• Develop custom timing scripts using tcl/perl scripts for special checks, data processing.

                  

  

Profile

  

  

In order to fulfil the role, we are looking for talented candidates with the following profile:

  

• CS/EE or background in areas related to digital or analog chip design

• 2+ years’ work experience

• Research and development experience in one or more of the following areas:

  • ASIC back-end design methodology: Knowledge of floor planning, physical design, timing, DFT, signal/power integrity, packaging, synthesis, and other back-end activities

  • EDA algorithm, tool, and methodology development.

  • Experience/knowledge in analog and mixed-signal IP design, test and evaluation with Bulk CMOS, BiCMOS, SiGe, or SOI technologies

  • Proficiency in Verilog/VHDL, and familiarity with programming and scripting languages is a significant plus

• Experience in one or some of the application domains, will be a plus

• High performance computing (servers) system, processor, chipset and ASICs

• Communication, networking and wireless applications

• Digital signal processing and RISC Processor architecture

• Digital media, audio/video graphic and gaming processing

• Consumer electronics applications

• High Speed Interface/Serdes applications

• Good software background and strong C/C++ skill

• Good English skills, communication skills, and willingness to work with a global team.

• Skill in other languages will be a plus.

• Good learning competency and ability to work in diverse areas in a flexible environment

                                    

Capgemini Engineering凯捷科技研发是全球工程研发 (ER&D) 服务的企业合作伙伴，基于其在数字化和软件领域的深厚行业知识及前沿技术积累，凯捷科技研发赋能客户实现数字世界和现实世界的融合，并结合集团其他部门的能力，加速其产业智能化的发展步伐。凯捷科技研发现有超过55,000名工程师和技术专家，遍布全球30多个国家，服务于航空、航天、国防、海军、汽车、铁路、基础设施与交通、能源、公用事业与化工、生命科学、通信、半导体与电子、工业与消费、软件与互联网等产业。

Capgemini Engineering是凯捷集团必不可少的一部分。凯捷是全球知名的企业合作伙伴，利用技术的力量改造和管理企业业务。其宗旨是通过技术释放人类能量，创造一个包容和可持续的未来。凯捷是一个负责任的多元化组织，在50余个国家拥有超过34万名团队成员。凭借其55余年的悠久历史和深厚的行业专业知识，在快速发展的云、数据、人工智能、互联连接、软件、数字工程和平台的创新世界推动下，凯捷深受客户信任，能够满足客户从战略、设计到运营的多方位业务需求。集团2021年全球收入为180亿欧元。