东莞招聘

  

The verification tasks include block level, chip level verification, test plan creation, scripting, coverage, regression run etc..
Requirements: The candidate is preferred to be MSEE with minimum of 3+ years, in digital ASIC/SOC design verification. More experience will be considered as senior engineer or lead. The candidate should have good understanding on ASIC/SOC design flow and should have: 0. Familiar with one of major verification languages: UVM, C, C++, SystemVerilog, Verilog 1. Good knowledge of design verification methodology, such as UVM or OVM and coverage driven verification methodology 2. Many experiences with simulation model creation and the testbench build 3. Strong RTL coding with Verilog and familiar with front-end design flow 4. Background in one of the area below will be a strong plus: a. Strong C/C++ software development experiences for ARM based SoC system b. Video, display, GPU, DDR, PCIe, USB etc.. 5. Be familiar with scripting language, such as Perl, C shell, Makefile.

  

Capgemini Engineering凯捷科技研发是全球工程研发 (ER&D) 服务的企业合作伙伴，基于其在数字化和软件领域的深厚行业知识及前沿技术积累，凯捷科技研发赋能客户实现数字世界和现实世界的融合，并结合集团其他部门的能力，加速其产业智能化的发展步伐。凯捷科技研发现有超过55,000名工程师和技术专家，遍布全球30多个国家，服务于航空、航天、国防、海军、汽车、铁路、基础设施与交通、能源、公用事业与化工、生命科学、通信、半导体与电子、工业与消费、软件与互联网等产业。

Capgemini Engineering是凯捷集团必不可少的一部分。凯捷是全球知名的企业合作伙伴，利用技术的力量改造和管理企业业务。其宗旨是通过技术释放人类能量，创造一个包容和可持续的未来。凯捷是一个负责任的多元化组织，在50余个国家拥有超过34万名团队成员。凭借其55余年的悠久历史和深厚的行业专业知识，在快速发展的云、数据、人工智能、互联连接、软件、数字工程和平台的创新世界推动下，凯捷深受客户信任，能够满足客户从战略、设计到运营的多方位业务需求。集团2021年全球收入为180亿欧元。