Sr. Physical Design Engineer 后端设计
新突思电子科技（上海）有限公司
- 公司规模：150-500人
- 公司性质：外资（欧美）
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2017-12-05
- 工作地点：成都
- 工作经验：5-7年经验
- 学历要求：硕士
- 语言要求：英语熟练
- 职位月薪：30-45万/年
- 职位类别：集成电路IC设计/应用工程师
职位描述
职位描述：
Key Areas of Responsibilities:
Physical Design for ASIC products
? Perform floor-planning, physical synthesis, clock tree and clock gating design, power gating, routing, layout, integration and physical verification
? Solve deep sub-micron design problems such as leakage, power, signal integrity, DFM, DFT etc.
? Independently assess and drive complex digital physical design projects
? Enhance IC physical design flow methodology
? Perform power, performance and area benchmark for new technology adoption
? Develop Perl/TCL/Shell scripts for flow and procedure automation
? Interact with Logic designers, AMS designers and internal/external IP teams
? Work proactively with EDA engineers and tool suppliers to debug tool functionality and bugs
? Work with Std Cells, Memory and I/O teams
? Support failure analysis
Required Skills and Attributes:
? BS in Electrical Engineering with 5-year experience, or equivalent MS degree
? Complete knowledge of full design IC implementation and signoff process including design constraint generation, RTL Synthesis, logic design, floor-planning, cell placement, cock tree creation, SDC, routing, optimization, timing/drc closure and design signoff
? Experienced with using Cadence Encounter, Synopsys ICC, ETS, Prime Time, PVS, QRC, Calibre, XRC, Hercules, StarRC etc.
? Proficient in STA, power analysis, DRC/LVS/PEX/DFM, noise, static and dynamic IR drop analysis
? Expertise in low power flow (power gating, multi-Vt, voltage islands, adaptive or dynamic voltage scaling etc)
? Good UNIX background and Perl/Shell/SKILL scripting skills
? Good written and verbal communication capability and proficient in both English and Mandarin
? Strong time management and multi-tasking skills that enable on-time delivery
? Motivated team player with customer and quality focus
? Analytical and persistent in resolving technical issues
? Possess strong work ethics with honesty and integrity
Preferred Skills:
? MS, PhD in Electrical Engineering, or equivalent
? Experienced in working with analog circuits and transistor level layout designers
? Familiar with design and layout of logic or analog circuits using Cadence Virtuoso or other tools
? Familiar with digital design tools such as RTL Compiler, DFT, MBIST etc.
Key Areas of Responsibilities:
Physical Design for ASIC products
? Perform floor-planning, physical synthesis, clock tree and clock gating design, power gating, routing, layout, integration and physical verification
? Solve deep sub-micron design problems such as leakage, power, signal integrity, DFM, DFT etc.
? Independently assess and drive complex digital physical design projects
? Enhance IC physical design flow methodology
? Perform power, performance and area benchmark for new technology adoption
? Develop Perl/TCL/Shell scripts for flow and procedure automation
? Interact with Logic designers, AMS designers and internal/external IP teams
? Work proactively with EDA engineers and tool suppliers to debug tool functionality and bugs
? Work with Std Cells, Memory and I/O teams
? Support failure analysis
Required Skills and Attributes:
? BS in Electrical Engineering with 5-year experience, or equivalent MS degree
? Complete knowledge of full design IC implementation and signoff process including design constraint generation, RTL Synthesis, logic design, floor-planning, cell placement, cock tree creation, SDC, routing, optimization, timing/drc closure and design signoff
? Experienced with using Cadence Encounter, Synopsys ICC, ETS, Prime Time, PVS, QRC, Calibre, XRC, Hercules, StarRC etc.
? Proficient in STA, power analysis, DRC/LVS/PEX/DFM, noise, static and dynamic IR drop analysis
? Expertise in low power flow (power gating, multi-Vt, voltage islands, adaptive or dynamic voltage scaling etc)
? Good UNIX background and Perl/Shell/SKILL scripting skills
? Good written and verbal communication capability and proficient in both English and Mandarin
? Strong time management and multi-tasking skills that enable on-time delivery
? Motivated team player with customer and quality focus
? Analytical and persistent in resolving technical issues
? Possess strong work ethics with honesty and integrity
Preferred Skills:
? MS, PhD in Electrical Engineering, or equivalent
? Experienced in working with analog circuits and transistor level layout designers
? Familiar with design and layout of logic or analog circuits using Cadence Virtuoso or other tools
? Familiar with digital design tools such as RTL Compiler, DFT, MBIST etc.
职能类别： 集成电路IC设计/应用工程师
关键字： 后端设计 Soc RTL Cadence Synopsys SDC
公司介绍
Synaptics is the pioneer and leader of the human interface revolution, bringing innovative and intuitive user experiences to intelligent devices. Synaptics’ broad portfolio of touch, display, biometrics, voice, audio, and multimedia products is built on the company’s rich R&D, extensive IP and dependable supply chain capabilities. With solutions designed for mobile, PC, smart home, and automotive industries, Synaptics combines ease of use, functionality and aesthetics to enable products that help make our digital lives more productive, secure and enjoyable. (NASDAQ: SYNA) *****************
联系方式
- 公司地址：地址：span牛顿路350号