Staff/Senior Design Verification Engineer
新突思电子科技（上海）有限公司
- 公司规模：150-500人
- 公司性质：外资（欧美）
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2017-12-05
- 工作地点：上海-浦东新区
- 工作经验：10年以上经验
- 学历要求：本科
- 语言要求：英语熟练
- 职位月薪：30-50万/月
- 职位类别：IC验证工程师
职位描述
职位描述：
Job Tasks
? Work with designer to get a full deep insight on the design and develop stressful test plan for SoC and IPs
? Build test bench and create testcase to ensure maximum coverage
? Run simulation in both RTL and netlist level, debug and fix issues, create test reports.
? Develop verification IP which can be reused at different level verification
? Co-work with FPGA engineer to prepare test vector, support test and debug
? SoC system performance profiling, system stress test
? Explore advanced verification methodology, optimize the verification process/environment to improve efficiency and quality
? Support DV manager to do the verification quality control and sign-off the DV task
Qualifications
Must Have
? MSEE/MSCS degree or equivalent
? Minimum 8 years’ experience in design verification field
? Good knowledge in SystemVerilog, C/C++ and UVM
? Good knowledge in the SoC architecture, AXI/AHB protocol. Experienced in full chip verification plan, execution and sign-off.
? Experienced in system performance test
? Strong communications skills and capability
? Self-motivated and good team player
Nice to have
? Strong Programming in Perl, Python
? Good digital signal processing background and be familiar with video processing algorithm, be familiar with MATLAB
? Experienced in low power verification
? Be familiar with FPGA debug.
Job Tasks
? Work with designer to get a full deep insight on the design and develop stressful test plan for SoC and IPs
? Build test bench and create testcase to ensure maximum coverage
? Run simulation in both RTL and netlist level, debug and fix issues, create test reports.
? Develop verification IP which can be reused at different level verification
? Co-work with FPGA engineer to prepare test vector, support test and debug
? SoC system performance profiling, system stress test
? Explore advanced verification methodology, optimize the verification process/environment to improve efficiency and quality
? Support DV manager to do the verification quality control and sign-off the DV task
Qualifications
Must Have
? MSEE/MSCS degree or equivalent
? Minimum 8 years’ experience in design verification field
? Good knowledge in SystemVerilog, C/C++ and UVM
? Good knowledge in the SoC architecture, AXI/AHB protocol. Experienced in full chip verification plan, execution and sign-off.
? Experienced in system performance test
? Strong communications skills and capability
? Self-motivated and good team player
Nice to have
? Strong Programming in Perl, Python
? Good digital signal processing background and be familiar with video processing algorithm, be familiar with MATLAB
? Experienced in low power verification
? Be familiar with FPGA debug.
职能类别： IC验证工程师
关键字： Soc simulation verificaiton IP System Verilog UVM
公司介绍
Synaptics is the pioneer and leader of the human interface revolution, bringing innovative and intuitive user experiences to intelligent devices. Synaptics’ broad portfolio of touch, display, biometrics, voice, audio, and multimedia products is built on the company’s rich R&D, extensive IP and dependable supply chain capabilities. With solutions designed for mobile, PC, smart home, and automotive industries, Synaptics combines ease of use, functionality and aesthetics to enable products that help make our digital lives more productive, secure and enjoyable. (NASDAQ: SYNA) *****************
联系方式
- 公司地址：地址：span牛顿路350号