Packaging Engineer研发封装工程师(2018年毕业生)
晟碟半导体(上海)有限公司
- 公司性质:外资(欧美)
- 公司行业:电子技术/半导体/集成电路
职位信息
- 发布日期:2017-07-16
- 工作地点:上海
- 招聘人数:1人
- 工作经验:无工作经验
- 学历要求:硕士
- 职位月薪:1-1.5万/月
- 职位类别:电子技术研发工程师
职位描述
职位描述:
Job Description:
Working with Program team and other Packaging Engineering team to assure the Quality of new Technology Programs and new PlatForms development.
1. PID Quality Control for new wafer technology:
o Thin Die Qual design and validation;
o PID Charz DOE design and validation;
o PID process change related Charz DOE design and validation;
o PID tape out involvement;
o PID design with Lesson Learnt and FMEA;
o PID PNTF, Statistic Design & Analysis, IVT, VECQ, ePPM Score card, Measurement Instruction, Validation, Toll Gate, etc.
2. New Technology Programs Design and Development Quality Assurance:
o TDW/TDS/EDS/MDS, PNTF, CFMEA, VECQ, Measurement Instruction, Statistic Design & Analysis, Toll Gate, Audit, Validation, etc.
3. New PlatForms Design and Development Quality Assurance
o Proposing, Verifying, Ground Rule, PNTF, PF-FMEA, VECQ, Measurement Instruction, Statistic Design & Analysis, Toll Gate, Audit, Validation, DI team, etc.
4. New Packages (retail) Design and Development Quality Assurance
o PDS signature, Recipe Baseline, TDCN, IVT, Toll Gate, etc.
5. TDCN and DCCB review committee.
6. Excursion/Abnormal Control
o RCA, Agile Team, DMAIC, etc.
7. Competitor Analysis for new Technology and PlatForm
o Flip Chip, Fan In/Out, 3D NAND, High capacity PKG, etc.
8. Charz Analysis
o FIB/SEM/EDX/3D X-ray/TEM/X-section/etc.任职资格Requirements:
? Master degree or above in Microelectronic science and technology or Material science and technology or Mechanical engineering or Electrical Engineering.
? English communication skills: CET-4 or above, be fluent both in oral and written English.
? Basic understanding of assembly process flow & materials and wafer fabrication processes.
? Basic knowledge of operation principle for NAND/DDR/ASIC.
? Basic Computer & Microsoft Office skills are required, AutoCAD/Cadence/JMP are preferred.
? Be capable of analyzing SEM/FIB/TEM/EDX results, operating is preferred.
? Ability to achieve results in a fast moving, dynamic environment.
? Ability to troubleshoot and analyze complex problems.
? Ability to multi-task and meet deadlines with team work.
? Open mind and positive communication with In-time feedback.
? Good Adoptability and Agility with fast changing environment.
? Self-motivated and self-directed, however, must have demonstrated ability to work well with people.
? A proven desire to work as a team member, both on the same team and cross team.
? Willingly creative and exceed.
? Excellent English communication (written and verbal) and interpersonal skills.
Be capable of occasionally over time work and oversea business travel.
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Job Description:
Working with Program team and other Packaging Engineering team to assure the Quality of new Technology Programs and new PlatForms development.
1. PID Quality Control for new wafer technology:
o Thin Die Qual design and validation;
o PID Charz DOE design and validation;
o PID process change related Charz DOE design and validation;
o PID tape out involvement;
o PID design with Lesson Learnt and FMEA;
o PID PNTF, Statistic Design & Analysis, IVT, VECQ, ePPM Score card, Measurement Instruction, Validation, Toll Gate, etc.
2. New Technology Programs Design and Development Quality Assurance:
o TDW/TDS/EDS/MDS, PNTF, CFMEA, VECQ, Measurement Instruction, Statistic Design & Analysis, Toll Gate, Audit, Validation, etc.
3. New PlatForms Design and Development Quality Assurance
o Proposing, Verifying, Ground Rule, PNTF, PF-FMEA, VECQ, Measurement Instruction, Statistic Design & Analysis, Toll Gate, Audit, Validation, DI team, etc.
4. New Packages (retail) Design and Development Quality Assurance
o PDS signature, Recipe Baseline, TDCN, IVT, Toll Gate, etc.
5. TDCN and DCCB review committee.
6. Excursion/Abnormal Control
o RCA, Agile Team, DMAIC, etc.
7. Competitor Analysis for new Technology and PlatForm
o Flip Chip, Fan In/Out, 3D NAND, High capacity PKG, etc.
8. Charz Analysis
o FIB/SEM/EDX/3D X-ray/TEM/X-section/etc.任职资格Requirements:
? Master degree or above in Microelectronic science and technology or Material science and technology or Mechanical engineering or Electrical Engineering.
? English communication skills: CET-4 or above, be fluent both in oral and written English.
? Basic understanding of assembly process flow & materials and wafer fabrication processes.
? Basic knowledge of operation principle for NAND/DDR/ASIC.
? Basic Computer & Microsoft Office skills are required, AutoCAD/Cadence/JMP are preferred.
? Be capable of analyzing SEM/FIB/TEM/EDX results, operating is preferred.
? Ability to achieve results in a fast moving, dynamic environment.
? Ability to troubleshoot and analyze complex problems.
? Ability to multi-task and meet deadlines with team work.
? Open mind and positive communication with In-time feedback.
? Good Adoptability and Agility with fast changing environment.
? Self-motivated and self-directed, however, must have demonstrated ability to work well with people.
? A proven desire to work as a team member, both on the same team and cross team.
? Willingly creative and exceed.
? Excellent English communication (written and verbal) and interpersonal skills.
Be capable of occasionally over time work and oversea business travel.
职能类别: 电子技术研发工程师
公司介绍
西部数据推动数据繁荣,缔造辉煌成就。无论在手机、云端抑或各个组织中,凡是数据所及之处,我们都在日复一日地推动必要的创新。无论是设备、系统、解决方案还是数据结构,我们都在不断进行着优化和调整,以期为充分发挥数据潜力创造合适的条件。
西部数据创新的技术和解决方案能帮助用户创建、保存、获取和改变日益增加的数据多样性。作为业内领先的解决方案提供商,我们有责任为重视数据的用户和系统提供更好的使用体验。西部数据公司以数据为中心的解决方案在WD,闪迪,G-Technology,Tegile和Upthere品牌下进行销售。
西部数据创新的技术和解决方案能帮助用户创建、保存、获取和改变日益增加的数据多样性。作为业内领先的解决方案提供商,我们有责任为重视数据的用户和系统提供更好的使用体验。西部数据公司以数据为中心的解决方案在WD,闪迪,G-Technology,Tegile和Upthere品牌下进行销售。
联系方式
- Email:sdss@Sandisk.com
- 公司地址:上海市闵行区江川东路388号 (邮编:200241)