赴新加坡IC设计/验证相关工程师职位
江苏亿涛对外经济合作有限公司
- 公司规模：少于50人
- 公司性质：民营公司
- 公司行业：专业服务(咨询、人力资源、财会)
职位信息
- 发布日期：2017-03-28
- 工作地点：国外
- 招聘人数：5人
- 工作经验：3-4年经验
- 学历要求：本科
- 语言要求：英语 熟练 普通话 精通
- 职位月薪：25000-29999/月
- 职位类别：集成电路IC设计/应用工程师 IC验证工程师
职位描述
职位描述：
赴新加坡IC设计/验证相关工程师职位
如有兴趣赴新加坡发展, 请联系
小刘 - 江苏亿涛对外经济合作有限公司
手机: 13913877072
QQ: 157827934
Email: ray@jsutop.com
职位1: Physical Verification CAD Engineer
Job Responsibilities:
1. Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
2. Co-work with Place & Route team to resolve full-chip layout integration issues.
3. Coordinates with internal IP owners on IP related issues.
4. Coordinates with Manufacturing Team on DRC related issues.
5. Provide automation solutions to improve efficiency in tape-out flow.
6. Report on tapeout issues.
7. Co-work with PDK team to code and maintain DRC/LVS/ANT/ERC/LPE/ESD rule deck for various processes
8. Develop layout implementation flow and physical verification flow
9. Co-work with QA team to reduce the PDKs/Rule deck defects
10. Implement automation scripts in C-shell and Perl
Requirements:
1. Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science
2. Familiar with IC Design front-to-backend flow
3. Preferably well-versed in Calibre, ICV, Assura, Star-RCXT
4. Proficient in script programming, such as, Tcl, Perl or C-shell
5. Proficient in UNIX (Linux) platforms
6. Strong communication skills, problem solving and analytical skills
职位2: Custom Layout Engineer
Job Responsibilities:
1. Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and milestones
2. Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow
3. Work closely with multi-functional teams to constantly optimize layout implementation for better power, performance, area and schedule
4. Responsible for in-house RF/Analog projects and IP/library developments
Requirements:
1. Bachelor’s degree in Electrical/Electronic/Computer Engineering
2. Proficient in Synopsys/Cadence layout editor and physical verification tools; analytical and skillful in DRC/LVS debugging
3. Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing and top-down integration flow
4. Have a good grasp of DRM of advanced node CMOS technologies
5. Team player and effective in cross-team communication and time management
6. Proficiency in script programming (eg. Tcl, Perl or C-shell) is a plus
7. Experienced candidate will be considered for senior position
举报
分享
赴新加坡IC设计/验证相关工程师职位
如有兴趣赴新加坡发展, 请联系
小刘 - 江苏亿涛对外经济合作有限公司
手机: 13913877072
QQ: 157827934
Email: ray@jsutop.com
职位1: Physical Verification CAD Engineer
Job Responsibilities:
1. Responsible for Full-chip Physical Verification Sign-off in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.
2. Co-work with Place & Route team to resolve full-chip layout integration issues.
3. Coordinates with internal IP owners on IP related issues.
4. Coordinates with Manufacturing Team on DRC related issues.
5. Provide automation solutions to improve efficiency in tape-out flow.
6. Report on tapeout issues.
7. Co-work with PDK team to code and maintain DRC/LVS/ANT/ERC/LPE/ESD rule deck for various processes
8. Develop layout implementation flow and physical verification flow
9. Co-work with QA team to reduce the PDKs/Rule deck defects
10. Implement automation scripts in C-shell and Perl
Requirements:
1. Bachelor/Masters Degree in Electrical/Electronics Engineering / Computer Science
2. Familiar with IC Design front-to-backend flow
3. Preferably well-versed in Calibre, ICV, Assura, Star-RCXT
4. Proficient in script programming, such as, Tcl, Perl or C-shell
5. Proficient in UNIX (Linux) platforms
6. Strong communication skills, problem solving and analytical skills
职位2: Custom Layout Engineer
Job Responsibilities:
1. Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and milestones
2. Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow
3. Work closely with multi-functional teams to constantly optimize layout implementation for better power, performance, area and schedule
4. Responsible for in-house RF/Analog projects and IP/library developments
Requirements:
1. Bachelor’s degree in Electrical/Electronic/Computer Engineering
2. Proficient in Synopsys/Cadence layout editor and physical verification tools; analytical and skillful in DRC/LVS debugging
3. Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing and top-down integration flow
4. Have a good grasp of DRM of advanced node CMOS technologies
5. Team player and effective in cross-team communication and time management
6. Proficiency in script programming (eg. Tcl, Perl or C-shell) is a plus
7. Experienced candidate will be considered for senior position
职能类别： 集成电路IC设计/应用工程师 IC验证工程师
关键字： 新加坡 IC 设计 验证 工程师
公司介绍
江苏亿涛对外经济合作有限公司，是从事对外经济合作的专业公司。立足于中国国内的广大市场，开发中国的各类人力资源优势，不断提高公司的服务水准，努力建立国际性的服务品牌，竭诚向国内外客户提供最优质的服务。 ？？2006年，中国劳动部批准为合格的境外就业中介机构。劳社境外就准字[2006]年452号。 ？？2009年，中国商务部批准为对外劳务合作经营资格企业，证书编号为J320020090005。 ？？2011年，江苏省商务厅换发对外劳务合作经营资格证书，证书编号为LW320020110003。 ？？2015年，成为中国对外工程承包协会理事会员。
联系方式
- Email：ray@jsutop.com
- 公司地址：地址：span首都国际机场T3航站楼