嵌入式硬件工程师Embedded Hardware(微软)
上海微创软件股份有限公司深圳分公司
- 公司规模:500-1000人
- 公司性质:外资(欧美)
- 公司行业:计算机软件
职位信息
- 发布日期:2013-09-04
- 工作地点:深圳
- 招聘人数:若干
- 工作经验:五年以上
- 学历要求:本科
- 语言要求:英语熟练
- 职位类别:高级硬件工程师 硬件工程师
职位描述
Design Verification Engineer/Surface
Role & Opportunity:
The responsibilities of this position are focused on specifying, designing (schematic capture, PCB layout , implementing and verifying the motherboard and other various sub-system boards that make up the Surface product. This work includes development of requirements and evaluating different solution for functionality, cost, and risk. The subsystems on the motherboard include (but are not limited to): High speed buses (front side bus, memory bus, PCIe bus, SATA bus, USB bus, I2S, I2C,UART,etc.), memory, Ethernet, Wi-Fi, processors, audio/video, system clocking, power and thermal management, and misc. analog/digital circuitry. The position involves working closely with industrial designers, electrical engineers, BIOS engineer, mechanical engineers, software engineers, test engineers, component engineers, and program managers.
Candidates should be able to apply core electrical engineering hardware and firmware skills to drive detailed problem solving on products within a technical team as well as manage broader industry standards, interoperability and compatibility testing with external development and test partners.
Qualifications:
Minimum BS in Electrical Engineering or Computer Engineering or related field.
Minimum of 5+ years’ experience contributing to the design and production of complex products in the electronics industry.
A solid understanding of core engineering principles, fundamental circuit design, and analytical techniques is required. Familiar with high speed design signal integrity issues, power distribution techniques, system clock & modern processors
Familiarity with embedded system architectures hardware and software, experience with implementation of high speed serial buses (SATA, PCIe, USB) and/or high speed parallel buses such as: memory bus (DDR2, GDDR3, etc.), CPU front side bus, Hyper transport, and/or voltage regulator/ power delivery design a plus.
Strong bench evaluation and in-lab debugging skills are required.
Hands-on board design experience, familiar with design tools including Cadence and Allegro.
Good understanding of electronic assembly processes
Conducting detailed failure analysis on mother board and computer external interface; working with manufacturing and engineering teams to put in corrective actions
Strong communication skills required, including the ability to clearly express technical concepts in verbal and written forms. Will need to communicate with team members is USA.
Must be able to plan work, and work to a plan adapting as necessary in a rapidly evolving environment.
Enthusiastic, motivated and self-driven.
Experience with computer mother board, firmware/UEFI, BIOS or FPGAs desired
Experience with Cadence desired
Design for manufacturing and test experience is required. Experience with CDM partners is desirable.
The ability to comprehend and assimilate technical concepts across multiple disciplines is a plus.
Domestic and international travel may be required.
________________________________________
In addition to the JD, below is excerpt from my new team charter specific to the role of the DVE (please note that there is some FTE responsibility included that the v- will not be doing.
Active Team Member
DVE/SDET will be active team member of the project team.
Attend meetings in person and via conference call.
Travel to Redmond as needed for continuity (this will be minimal for v-)
Attend builds at JDM1
External Device Interface Verification.
Take ownership of external interface (connector) verification that has been outsourced to China or Taiwan.
USB
HDMI
SD
DP
JDM1 DVE Testing Activates
Responsible for overseeing all DVE testing at JDM1
Ensure tests are done correctly. Validate test methods.
Audit testing activities.
Review test report and ensure meets MS standards.
For tests developed by Redmond DVE team members.
Learn the tests while Redmond Team Members is at JDM1.
Assume ownership of testing after Team Member returns to Redmond.
Accountability for SOW with JDM1 test activities
Build Test Capability As Needed
Where it makes since, build in house test capability.
Currently building capability for HDMI, USB 2.0 and 3.0 and DP electrical testing at MACH.
Role & Opportunity:
The responsibilities of this position are focused on specifying, designing (schematic capture, PCB layout , implementing and verifying the motherboard and other various sub-system boards that make up the Surface product. This work includes development of requirements and evaluating different solution for functionality, cost, and risk. The subsystems on the motherboard include (but are not limited to): High speed buses (front side bus, memory bus, PCIe bus, SATA bus, USB bus, I2S, I2C,UART,etc.), memory, Ethernet, Wi-Fi, processors, audio/video, system clocking, power and thermal management, and misc. analog/digital circuitry. The position involves working closely with industrial designers, electrical engineers, BIOS engineer, mechanical engineers, software engineers, test engineers, component engineers, and program managers.
Candidates should be able to apply core electrical engineering hardware and firmware skills to drive detailed problem solving on products within a technical team as well as manage broader industry standards, interoperability and compatibility testing with external development and test partners.
Qualifications:
Minimum BS in Electrical Engineering or Computer Engineering or related field.
Minimum of 5+ years’ experience contributing to the design and production of complex products in the electronics industry.
A solid understanding of core engineering principles, fundamental circuit design, and analytical techniques is required. Familiar with high speed design signal integrity issues, power distribution techniques, system clock & modern processors
Familiarity with embedded system architectures hardware and software, experience with implementation of high speed serial buses (SATA, PCIe, USB) and/or high speed parallel buses such as: memory bus (DDR2, GDDR3, etc.), CPU front side bus, Hyper transport, and/or voltage regulator/ power delivery design a plus.
Strong bench evaluation and in-lab debugging skills are required.
Hands-on board design experience, familiar with design tools including Cadence and Allegro.
Good understanding of electronic assembly processes
Conducting detailed failure analysis on mother board and computer external interface; working with manufacturing and engineering teams to put in corrective actions
Strong communication skills required, including the ability to clearly express technical concepts in verbal and written forms. Will need to communicate with team members is USA.
Must be able to plan work, and work to a plan adapting as necessary in a rapidly evolving environment.
Enthusiastic, motivated and self-driven.
Experience with computer mother board, firmware/UEFI, BIOS or FPGAs desired
Experience with Cadence desired
Design for manufacturing and test experience is required. Experience with CDM partners is desirable.
The ability to comprehend and assimilate technical concepts across multiple disciplines is a plus.
Domestic and international travel may be required.
________________________________________
In addition to the JD, below is excerpt from my new team charter specific to the role of the DVE (please note that there is some FTE responsibility included that the v- will not be doing.
Active Team Member
DVE/SDET will be active team member of the project team.
Attend meetings in person and via conference call.
Travel to Redmond as needed for continuity (this will be minimal for v-)
Attend builds at JDM1
External Device Interface Verification.
Take ownership of external interface (connector) verification that has been outsourced to China or Taiwan.
USB
HDMI
SD
DP
JDM1 DVE Testing Activates
Responsible for overseeing all DVE testing at JDM1
Ensure tests are done correctly. Validate test methods.
Audit testing activities.
Review test report and ensure meets MS standards.
For tests developed by Redmond DVE team members.
Learn the tests while Redmond Team Members is at JDM1.
Assume ownership of testing after Team Member returns to Redmond.
Accountability for SOW with JDM1 test activities
Build Test Capability As Needed
Where it makes since, build in house test capability.
Currently building capability for HDMI, USB 2.0 and 3.0 and DP electrical testing at MACH.
公司介绍
上海微创软件股份有限公司于2002年由微软与上海市政府共同创办,是微软在华投资的***家合资公司。 微创始终秉承高标准的服务品质与“成就客户”的服务理念,在全球设有20余处交付中心,分布在中国、美国、日本、澳大利亚,与2500余家企业与政府客户达成了长期、稳定、友好的合作。
联系方式
- Email:v-wsfthr@microsoft.com
- 公司地址:深圳市南山区科技园科苑路科兴科学园A4栋1502室 (邮编:518057)
- 电话:15811901164