集成电路版图设计工程师-IC physical design engineer
富士通半导体设计（成都）有限公司
- 公司规模：150-500人
- 公司性质：外资(非欧美)
- 公司行业：电子技术/半导体/集成电路
职位信息
- 发布日期：2013-02-05
- 工作地点：成都
- 招聘人数：1
- 工作经验：三年以上
- 学历要求：本科
- 语言要求：英语良好
- 职位类别：版图设计工程师
职位描述
Job Responsibility
1. Cooperate with logical engineers for product spec definition
2. Hands on chip physical designs from netlist to GDSII, including floor planning, power planning, Place & Route, CTS, power analysis, timing closure, cross talk analysis, and physical verification
3. Create/maintain/optimize chip physical design flow
Technical Capability Requirement
1. Hands on experience in complete full chip Netlist to GDS implementations (floor-plan, power plan, P&R, CTS, timing closure, cross talk analysis, power analysis and PV checking)
2. Have thorough knowledge on CTS, STA and cross talk analysis
3. Good knowledge on CMOS device structure, process technology, EMI/EMS, latch-up, ESD
4. Low power and CPF experience is a plus
5. Familiar with physical design EDA tools, Unix/Linux environment
6. Good scripting experience in C-shell, Perl and Tcl
General Capability Requirement
1. 3 years or above work experience in P&R and silicon tape-out
2. Bachelor or above degree of Microelectronic or Electronic and Information Engineering
3. Good verbal and written English communication skill
4. Japanese language is a plus
Comprehensive Quality Requirement
1. Self-motivated
2. Good team work spirit
1. Cooperate with logical engineers for product spec definition
2. Hands on chip physical designs from netlist to GDSII, including floor planning, power planning, Place & Route, CTS, power analysis, timing closure, cross talk analysis, and physical verification
3. Create/maintain/optimize chip physical design flow
Technical Capability Requirement
1. Hands on experience in complete full chip Netlist to GDS implementations (floor-plan, power plan, P&R, CTS, timing closure, cross talk analysis, power analysis and PV checking)
2. Have thorough knowledge on CTS, STA and cross talk analysis
3. Good knowledge on CMOS device structure, process technology, EMI/EMS, latch-up, ESD
4. Low power and CPF experience is a plus
5. Familiar with physical design EDA tools, Unix/Linux environment
6. Good scripting experience in C-shell, Perl and Tcl
General Capability Requirement
1. 3 years or above work experience in P&R and silicon tape-out
2. Bachelor or above degree of Microelectronic or Electronic and Information Engineering
3. Good verbal and written English communication skill
4. Japanese language is a plus
Comprehensive Quality Requirement
1. Self-motivated
2. Good team work spirit
公司介绍
富士通半导体设计（成都）有限公司是日本富士通在中国的半导体研发公司。公司前身是一家国内数字音视频芯片研发公司，于2001年11月成立，在2006年富士通半导体入股后，强化核心技术发展、产品规划、及专业化等方面的管理。现在富士通半导体设计（成都）有限公司为富士通半导体有限公司的全资子公司，是一家年轻并富有活力的公司,领导层由拥有超过20年开发和国际公司管理经验的人员组成。主要从事数字音视频专用标准芯片(ASSP)(STB/DTV)、单片机芯片（MCU）和模拟芯片(Analog)的设计、开发、配套解决方案及相关高新技术的研发，并以更强的研发力量，进一步为中国市场供应更贴近本地需求产品。
公司地址:成都市高新区高朋大道3号B座5-6F
电 话: 028-85150023
邮 箱: hr_fsdc@cn.fujitsu.com
公司地址:成都市高新区高朋大道3号B座5-6F
电 话: 028-85150023
邮 箱: hr_fsdc@cn.fujitsu.com
联系方式
- Email：fsdc@cn.fujitsu.com