成都招聘

1. Responsible for design of DDR3/4 controller, including specification, architecture, micro-architecture, implementation (using Verilog), and verification;

2. Co-work with analog team for DDR PHY design;

3. RTL Coding, including block design, top level design, DFT/Lower power design in SoC;

4. Integrate ddr controller to SoC, clock & reset structure design, chip debugging, failure analysis;

5. Support physical layout team on analog macro integration and synthesis/timing analysis.

Location:Shanghai/Chengdu

Qualifications:

1. Master or above in EE;

2. Solid understanding of digital design is a must, at least 3+ years DDR/PHY work experience;

3. Be familiar with all stages of the ASIC design flow (including specification and design implementation);

4. Be familiar with SOC system architecture;

5. Skilled in verilog and system Verilog language, vcs/nc verilog sim tool;

6. Self motivated, good communication skill and team work spirit.

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