成都招聘

Responsibilities：

1.Responsible for SoC chip physical implementation flow development and optimization;

2.Build up the back-end design team to support the physical implementation for 28nm or above process ；

3.Define the signoff target and checklist of each stage to ensure physical design quality control；

4.lead the back-end design team to finish the physical design of the SoC production chip ；

5.Supports SIFIVE U.S. CSOC team to deliver qualified results to customers quickly；

6.Co-work with SoC team to develop an advanced SoC design methodology and tools support from Spec-in to Silicon.

Qualifications:

1.More than 10 years of practical experience in physical design, bachelor or above, master degree is preferred;

2.Proficient in the SoC/chip design flow from Netlist to GDS;

3.Familiar with the PR/PV/signoff tools of mainstream EDA vendor;

4.Strong experience in low power design methodology e.g. Power gating, DVFS, etc;

5.Proficiency in the Shell/TCL/Perl/Python or other similar programming language programming and the establishment of automated design process;

6.5+ projects of independent or top-level physical design successful story;

7.Self-driven and team-work spirit, strong verbal and written communication skills in Chinese and English. Big Plus：

8.Experience in 16nm or 14nm physical design;

9.Experience in High-speed circuit physical implementation, e.g. DDR PHY, SerDes, etc;

10.Experience in Front-end design or RTL coding;

11.Experience in Customer Layout/Physical design for analog circuit.

StarFive是基于免费且开放的RISC-V指令集架构的商业化处理器核心IP、开发工具和芯片解决方案的领导者。 在RISC-V开创者和业内资深专家组成的团队领导下，StarFive帮助SoC设计人员缩短产品上市时间，以及通过定制的开放式架构处理器内核降低成本，同时，使系统设计人员能够构建基于RISC-V的定制半导体，从而实现芯片优化。

上海赛昉科技有限公司成立于2018年8月24日，公司基于RISC-V的开源生态并在RISC-V开创者和业内资深专家组成的团队领导下，利用领先的RISC-V内核定制技术和敏捷设计方法，成为具有国内自主可控，有龙头作用的RISC-V解决方案提供商；同时利用自主知识产权针对AI-IOT的关键应用领域，通过平台化、模板化的设计理念，实现垂直领域的核心技术整合，提供相关领域的系列化芯片及其解决方案，创造一种新的商业模式，成为对应领域的技术主导者和芯片与方案的主流供应商。