成都招聘

Responsibilities

1. Function/IP module coding and data path simulation
2. Chip level design and coding with good coding style
3. Co-work with software team to identify architecture requirements
4. Co-simulation with driver software program
5. Documentation for design spec in module level and chip level
6. IP module integration with direction of integration guide
7. FPGA prototyping development and debug
8. Evaluation of different architecture solutions
9. Define architecture of the CPU core and various hardware components surrounding the CPU, like local memory, interconnect and crypto accelerators

Qualifications

1. Familiar with Tilelink/AMBA/AXI bus protocol
2. 4+ years of relevant experience on IP based front-end design
3. Familiar with EDA tools of simulator and synthesis, spyglass,
4. Experience with C/C++ program for driver or algorithm implementation
5. Experience of FPGA design and debug with JTAG
6. Good coding style for RTL design
7. Good people and communication skills in Mandarin and English

Big Plus

1. Familiar with foundry lib, IP and process technology limitation
2. Familiar with tool chain (RTL, P&R, timing analysis/closure, power analysis, etc.)
3. Knowledge or project experiences of RISCV CPU
4. Knowledge of project experiences on SystemC modeling
5. Interest and experience for IP and chip design with chisel
6. Broad understanding to computer security and crypto algorithms like AES/SHA/RSA/ECC

StarFive是基于免费且开放的RISC-V指令集架构的商业化处理器核心IP、开发工具和芯片解决方案的领导者。 在RISC-V开创者和业内资深专家组成的团队领导下，StarFive帮助SoC设计人员缩短产品上市时间，以及通过定制的开放式架构处理器内核降低成本，同时，使系统设计人员能够构建基于RISC-V的定制半导体，从而实现芯片优化。

上海赛昉科技有限公司成立于2018年8月24日，公司基于RISC-V的开源生态并在RISC-V开创者和业内资深专家组成的团队领导下，利用领先的RISC-V内核定制技术和敏捷设计方法，成为具有国内自主可控，有龙头作用的RISC-V解决方案提供商；同时利用自主知识产权针对AI-IOT的关键应用领域，通过平台化、模板化的设计理念，实现垂直领域的核心技术整合，提供相关领域的系列化芯片及其解决方案，创造一种新的商业模式，成为对应领域的技术主导者和芯片与方案的主流供应商。