成都招聘

Responsibilities:

1. Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios

2. Create verification environment or test bench using System Verilog, UVM and/or System C

3. Identify and write all types of coverage measures for stimulus and corner-cases

4. Debug tests with design engineers to deliver functionally correct design blocks

5. Responsible for SoC's IP Level and Top Level verification, Pre-sim and Post-sim verification as owner

6. Build test cases, analyze validation results, and improve validation quality

7. Close coverage measures to identify verification holes and to show progress towards tape-out

Qualifications:

1. BS degree or equivalent practical experience. MS in EE or CS is preferred

2. 3+ years of relevant experience on IP based SoC verification

3. Familiar with Tilelink/AMBA/AXI bus protocol

4. Experience with verification methodology such as UVM/OVM/VMM/SystemC/C++

5. Experience with the full verification life cycle and experience with functional coverage

6. Experience with function verification for common SoC building blocks and verification ip: I2C/UART/SPI/I2S/USB, etc.

7. Strong problem solver, communicator and team player

8. Good people and communication skills in Mandarin and English

9. Scripting skills in Perl, tcl, shell, etc.

StarFive是基于免费且开放的RISC-V指令集架构的商业化处理器核心IP、开发工具和芯片解决方案的领导者。 在RISC-V开创者和业内资深专家组成的团队领导下，StarFive帮助SoC设计人员缩短产品上市时间，以及通过定制的开放式架构处理器内核降低成本，同时，使系统设计人员能够构建基于RISC-V的定制半导体，从而实现芯片优化。

上海赛昉科技有限公司成立于2018年8月24日，公司基于RISC-V的开源生态并在RISC-V开创者和业内资深专家组成的团队领导下，利用领先的RISC-V内核定制技术和敏捷设计方法，成为具有国内自主可控，有龙头作用的RISC-V解决方案提供商；同时利用自主知识产权针对AI-IOT的关键应用领域，通过平台化、模板化的设计理念，实现垂直领域的核心技术整合，提供相关领域的系列化芯片及其解决方案，创造一种新的商业模式，成为对应领域的技术主导者和芯片与方案的主流供应商。