成都招聘

Focus on analog/digital mixed and IOT IP and Chip verification. The engineers need to act as a strong team member and contributor, who also need to collaborate with digital F.E team closely.

Responsibilities:

• Be in charge of  IP and SOC verification
• Be in charge of developing test and regression plans.
• Be in charge of designing and developing verification environment and test cases
• Be in charge of running RTL and gate-level simulations/regression.
• Be in charge of code/functional coverage development, analysis and closure.

Requirements:

• Minimum of 3 years' design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
• Knowledge in ASIC/FPGA design process and verification tools/env (UVM/OVM…).
• Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
• Good IC verification skills and basic knowledge of logic or circuit design, and problem solving skills.
• Self-motivated, good communication skill and team work spirit.
• Fluent in both English and Chinese.
• Scripting and automation skills (TCL, Perl, Makefile etc) is a plus;
• Familiar with C/C++ is a plus.
• Knowledge of USB/PCIE/MIPI, ARM based SoC and design experience is a plus.