成都招聘

Responsibilities:

• Comprehend the SoC clock structure and working mode and prepare the SDC file for SoC design.
• Prepare the DFT plan for the SoC design.
• SCAN/MBIST/BSD insertion and synthesize methodology for Flatten/Hierarchical design.
• Pre/Post simulation for test patterns.
• Cooperate with timing engineer for timing signoff (STA).
• Analog IP test implementation and simulation.
• Support ATE engineer for chip testing debug, and analyze ATE log file to locate root cause of failure.
• Formal check of RTL and net list.

Requirements:

• Bachelor's degree or above, major in EE, CS or relevant.
• Above 5 years' work experience to the one with Bachelor's degree and above 3 years with Master's degree is required for Senior Engineer position.
• Skilled in SoC PPA, better for low power design.
• Improve low test coverage to achieve higher coverage.
• Skilled in CSH/Perl/TCL scripts.
• Be familiar with concept of SoC and P&R physical implementation.
• Fluent in both English and Chinese.
• Good team work spirit.